Delay Calculations

Section 6.1-6.4
Load Capacitance Calculation
C
load
=C
self
+C
wire
+C
fanout
Fanout Capacitance
Fanout Gate Capacitance
C
fanout
: fanout capacitance due to the inputs of
subsequent gates, C
G
.

C
fanout
=C
G1
+C
G2
+C
G3
.
Assumption: Each fanout is an inverter.
Input Capacitance Calculation
C
OL
: overlap capacitance
C
GN
, C
GP
: Thin Oxide Capacitance
Worst Case Analysis Assumption
The thin-oxide capacitance is voltage
dependent.
The worst case analysis uses C
ox
WL to
compute its worst case value.
Thin Oxide Capacitance:C
g
C
G
=WLC
ox
=WL(
ox
/t
ox
)=WC
g
Unit of C
g
: fF/m
[Worst Case Analysis]
C
g
tox L Cg
110 nm 5 1.61 fF/m
7.5 nm 0.35 m 1.65 fF/m
2.2 nm 0.1 m 1.61 fF/m
Cg is approximately 1.61 fF/m for the last 25 years.
Exception: the 0.18 m process, which has a Cg of 1.0 fF/ m.
[Worst Case Analysis]
Thin Oxide Capacitance:C
ol
Components of C
ol
C
ol
=C
f
+C
ov
C
f
:fringing capacitance
C
ov
: overlap capacitance
Redefine C
g
For 0.13 m,
C
g
(due to t
ox
alone): 1.6 fF/m [Hodges, p.72]
C
ol
(due to C
ov
and C
f
): 0.25 fF/ m [Hodges, p.80]
Redefine Cg [Hodges, p.259] as
C
g
=C
ox
L+2C
ol
C
g
=1.6 fF/m+ 2 0.25 fF/m=2 fF/m
C
g
has been constant for over 20 years
Multipy Cg by W to obtain the total capacitance
due to t
ox
, C
ov
and C
f


[Worst Case Analysis]
[Worst Case Analysis]
Gate Capacitance of an Inverter
C
G
=C
g
(W
n
+W
p
)
C
G
=2fF/m(W
n
+W
p
)

[Worst Case Analysis]
Input Capacitance of a
3-input NAND Gate
2W
2W
2W
3W
3W
3W
C
G
=C
g
(W
n
+W
p
)=C
g
(3W+2W)= C
g
(5W)
Fanout Gate capacitance of n Inverters
C
fanout
=2fF/m[(W
n
+W
p
)
1
+(W
n
+W
p
)
2
(W
n
+W
p
)
n
]


[Worst Case Analysis]
For NANDs, NORs, apply the
above equation with appropiate widths.
Self-Capacitance Calculation
1. Eliminate capacitors not connected to the output
2. Assume the transistors are either on (Saturation) or off (Cutoff).
3. C
GD
is negligible in either saturation or cutoff.
Calculation of Self-Capacitance of an
Inverter
C
self
=C
DBn
+C
DBP
+2C
OL
+2C
OL
C
DBn
=C
jn
W
n
C
DBp
=C
jp
W
p
C
OL
=C
ol
W
C
self
=C
jn
W
n
+C
jp
W
p
+2C
ol
(W
n
+W
p
)

Assume C
jn
=C
jp
C
self
=C
eff
(W
n
+W
p
)
For 0.13: C
eff
=1 fF/m [Hodges,
p. 261]
Self-Capacitance of a NOR
Condition:
A=0
B=01
CDB4, CSB3 do not need to be charged.NOT THE WORST CASE
CDB3 is charged, while CDB1 and CDB2 are discharged.
To avoid double counting, CDB1 and CDB2 will be called CDB12.
Self-Capacitance of NOR
Constant
Voltage at X
Self-Capacitance of a NOR
CDB4 and CSB3 need to be charged
CDB3 is charged, while CDB1 and CDB2 are
discharged
WORST
CASE!!
Self-Capacitance of NOR

WORST
CASE!!
Wire Capacitance
Ignore wire capacitance if the length of a wire
is less than a few microns.
Include wires longer than a few microns
C
wire
=C
int
L
wire
C
int
=0.2 fF/um
For very long wires use distributed model
Example 6.4
Capacitance Calculation for Inverter
Propagation Delay
Conclusion
Propagation delay depends on the arrival time
of inputs
In a series stack, the delay increases as the
late arriving input is further from the
output.



Sequence:
A: charges X
B: charges Y
C: discharges X, Y, CL Worst Case
Sequence:
C: discharges X, (if any)
B: discharges Y (if any)
A: discharges CL
Improved!
Design Strategy 1
Reorder the inputs so that
the earliest signal arrive lower in the stack
The latest signals arrive near the top of the
stack
Design Strategy 2
To reduce delay:
W
C
>W
B
>W
A
Problem:
Device capacitance are increased as the
device sizes are increased.
Delay Calculation with Input Slope
Improve Delay Calculation with Input
Slope
i
out
=i
NMOS
-i
PMOS
1. Select V
in
and V
out
2. Calculate i
NMOS
and i
PMOS
3. Calculate i
out
Inverter Output Current as a function
of V
out
and V
in
Simplified Inverter Output Current as a
function of V
out
and V
in
Example 6.5
Compute the delay (t
PHL,step
) of a CMOS
inverter due to a step input

Compute the delay (t
PHL,step
) of a CMOS
inverter due to an input ramp with a rise time
of t
r

Conclusion from Example 6.5
t
ramp
=t
ramp
+t
step


t
step
=0.7RC
t
ramp
depends on the t
r
of the driving circuit.
t
ramp
=0.7RC/2=0.3RC

Assumption: the t
r
is equal to 2t
PLH
Inverter Chain Delay for a Ramp Input
Example 6.6