DESIGN OF LOW POWER AND AREA

EFFICIENT TEST PATTERN

GENERATOR USING ALU

PRESENTED BY,
S.SELVI
UNDER THE GUIDANCE OF
MRS.S.KALYANI M.E,MISTE
HOD/ECE DEPARTMENT

ABSTRACT
TEST PATTERN GENERATION
-Weighted test pattern generation.
Generating TV Using arithmetic functions.
ALU as test pattern generator.
Addition more energy and time efficient.
Using the newly proposed carry select adder.

INTRODUCTION
Pseudorandom test pattern generators.
Why 3 weight assignment?
Why ALU as TPG?

EARLIER METHODS
Accumulator based test pattern generation
scheme
Accumulator based weighted test pattern
generation
Accumulator based 3-weight test pattern
generation

LITERATURE SURVEY
M. B. Santos, I. C. Teixeira, J. P. Teixeira, S. Manich, R. Rodriguez , and J. Figueras,
RTL level preparation of high-quality/low-energy/low-power BIST,
in Proc. Int. Test Conf., 2002, pp. 814823.

OBJECTIVE:
To drive innovative ,high quality , lower energy & lower
power BIST.

DESCRIPTION:

Test is generated at RTL level, reused to cover physical defects.

Mask based BIST is modeled.
& parameters are calculated for Power/Energy estimation. Also
static probability p and transition density D are calculated.

ADVANTAGE:
Achieves better defect coverage (DC).

DRAWBACK:
Increased Si area.

LITERATURE SURVEY
A. Rashid Mohamed, Z. Peng, and P. Eles,
A wiring-aware approach to minimizing built-in self-test overhead,
J. Comput. Sci. Technol., vol.20, no. 2, pp. 216223.

OBJECTIVE:
To minimize cost and area of BIST.

DESCRIPTION:

BIST at high level synthesis more Si area due to interconnects.

Analyse a problem in SDFG insert BIST modules in the design.
Simulated Annealing is used.
TPG is converted into BILBO.

ADVANTAGE:
Wiring cost is minimized.

DRAWBACK:

BILBO is larger than the TPG.

Use of extra hardware for BIST.

LITERATURE SURVEY
Sanjay Gupta , Janusz Rajski , Jerzy Tyszer ,
Test Pattern generation based on Arithmetic operations in
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computeraided designPages 117 - 124

OBJECTIVE:
To use already existing adders in data path for TPG.

DESCRIPTION:

First paper to give idea about using arithmetic units as TPG.

Parallel compaction of test responses - existing accumulators
with minimal area overhead, no performance degradation.

ADVANTAGE:

Low Hardware overhead.

No extra hardware for BIST.

DRAWBACK:
No impact on improving the performance of the circuit in terms
of speed.

LITERATURE SURVEY
S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, and J.Figueras,
On the selection of efficient arithmetic additive test pattern generators,
in Proc. Eur. Test Workshop, 2003, pp. 914.

OBJECTIVE:
To use existing internal data paths for TPG.

DESCRIPTION:
AdTPG Configuration triplet
seed , increment , number of times increment is done.
LUCSAM greedy algorithm to generate efficient triplet.
Specified fault coverage is achieved.

ADVANTAGE:
Memory size is reduced.

DRAWBACK:
Algorithm takes long run time.

LITERATURE SURVEY
S. Manich, L. Garcia, L. Balado, J. Rius, R. Rodrguez, and J. Figueras,
Improving the efficiency of arithmetic BIST by combining targeted and general purpose patterns,

presented at the Des. Circuits Integr. Syst. (DCIS), Bordeaux, France, 2004.

OBJECTIVE:
To achieve a better quality of tests by using new TPG methods.

DESCRIPTION:
Two types of patterns-

Target Purpose Patterns SI triplet

General Purpose Patterns SS triplet
LUCSAM+ Algorithm is designed.

ADVANTAGES:
Better performance than LUCSAM algorithm.

DRAWBACK:
Limited to combinational circuits only.
Time taken is more.

LITERATURE SURVEY
A.Stroele,
A self test approach using accumulators as test pattern generators,
in Proc. Int. Symp. Circuits Syst. , 1995, pp. 21202123.

OBJECTIVE:
To avoid performance degradation due to BIST by using ALU
as TPG.

DESCRIPTION:

Analyse various test patterns.

Accumulators with binary adder.
Accumulators with one`s complement adder.

ADVANTAGES:
Reduces additional test registers.

DRAWBACK:
Test time is comparatively long and no impact on delays.

LITERATURE SURVEY
I. Voyiatzis, D. Gizopoulos, and A. Paschalis,
Accumulator-based 3 weight pattern generation,
IEEE Trans. VLSI Syst. , vol. 20, no. 2, pp. 357-361, Feb. 2012.

OBJECTIVE:
To use 3 weight test pattern generation.

DESCRIPTION:
Assign 3 weights for the test inputs.
Designed for ISCAS C17 benchmark circuit.
Uses speed efficient parallel prefix adders.

ADVANTAGE:
Use of high speed adders.
No redesign of accumulator.
Comparatively less delay.

DRAWBACK:
More area is occupied.

ISCAS C17 BENCHMARK CIRCUIT

TEST SET FOR C17

S1 = { T1,T4 } , S2 = { T2,T3 }
W(S1) = { - , - , 1 , - , 1 }
W(S2) = { - , - , 0 , 1 , 0}

3-WEIGHTED TEST PATTERN

GENERATION
Weight 1 - I/P is constantly derived by 1
Weight 0 - I/P is constantly derived by 0
Weight 0.5 - I/P is pseudorandomly generated.

TRUTH TABLE OF FULL ADDER

ACCUMULATOR CELL

CONFIGURATIONS OF THE
ACCUMULATOR CELL

EXISTING SCHEME

PROPOSED METHOD
Designing the newly proposed Carry Select
Adder.
Design the whole system using the newly
proposed CSA.
Estimate the performance of newly designed
TPG in terms of Area and Delay consumed.

PROPOSED SCHEME

REGULAR CSA

PROPOSED CARRY SELECT ADDER

TOOLS USED
SYNTHESIS TOOL
Xilinx ISE 8.2 i Software
SIMULATION TOOL
Modelsim SE 10.1 d Software

SIMULATION RESULT

COMPARISON RESULT

NEWLY PROPOSED CSLA

In earlier proposed CSLA, delay is present.
In order to have a
b/w area , power and
delay D-Latch is used.

D-LATCH

NEWLY PROPOSED CSLA

TIMING DELAY
For Modified CSLA 18.150 ns
For Newly Proposed CSLA -3.150 ns

REFERENCES

Antonis Paschalis, Ioannis Voyiatzis, and Dimitris Gizopoulos,Accumulator based 3

weight pattern generation, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20,
no. 2, pp. 357361, Feb. 2012.
E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, An ef-cient seeds selection
method FOR lfsr-based test-per-clock BIST, in Proc. Int. Symp. Quality Electron. Des.
, 2002, p. 261.
S. Manich, L. Garcia, L. Balado, J. Rius, R. Rodrguez, and J. Figueras,Improving the
efciency of arithmetic bist by combining targeted and general purpose patterns,
presented at the Des. Circuits Integr. Syst. (DCIS), Bordeaux, France, 2004.
S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, and J.Figueras, On
the selection of efcient arithmetic additive test pattern generators, in Proc. Eur.
Test Workshop , 2003, pp. 914.
A. Rashid Mohamed, Z. Peng, and P. Eles, A wiring-aware approach to minimizing
built-in self-test overhead, J. Comput. Sci. Technol. , vol. 20, no. 2, pp. 216223.
A. Stroele, A self test approach using accumulators as test pattern generators, in
Proc. Int. Symp. Circuits Syst., 1995, pp. 21202123.

QUERIES?

THANK YOU