Now we have understood,

For any signal to be considered as logic 0 and logic 1, it should be in the NML and
NMH ranges, respectively

12/16/2014

Now we have understood,

For any signal to be considered as logic 0 and logic 1, it should be in the
NML and NMH ranges, respectively

Now, let us understand the factors affecting the voltage levels to vary from this range
12/16/2014

Ideal
Switching
Activity

Actual
Switching
Activity

Switching Activity of a Device is one of the factors which affects the voltage levels of
Input/Output signals

Vdd

Poly Gate

PMOS P Diff

Out

In

NMOS N Diff

Vss
Lets understand the internal process while Switching Activity happens in a Device

Vdd

Poly Gate

PMOS P Diff
Out

In

NMOS N Diff

Vss

PMOS
Consider the MOS device, to understand the actual scenario

NMOS

PMOS

Lets revise MOS device characteristics

NMOS

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

MOS device characteristics

G
Vgs

NMOS

Vgs is the Voltage between gate and source

MOS device characteristics

G
Vgs

NMOS

MOS device characteristics

G
Vgs

Vgs < VT (Threshold Voltage)

S
S

NMOS

If Vgs

is

less then VT , the NMOS will act as Open Switch

MOS device characteristics

G
Vgs

Vgs > VT (Threshold Voltage)

S
S

NMOS

If Vgs

is

greater then VT , the NMOS will act as Closed Switch

MOS device characteristics

G
Vgs

Vgs > VT
S

NMOS

MOS device characteristics

G
Vgs

Vgs > VT
S

NMOS

When MOSFET is ON, it can be modeled as a Resistor with switch closed

MOS device characteristics

G
Vgs

Vgs > VT
S

NMOS

When MOSFET is ON, it can be modeled as a Resistor with switch closed

When MOSFET is OFF, it can be modeled as an open switch

When MOSFET is ON, it can be modeled as a Resistor with closed switch

When MOSFET is ON, it can be modeled as a Resistor with switch closed

PMOS acts as Logic 0

NMOS acts as Logic 1

When MOSFET is ON, it can be modeled as a Resistor with switch closed

PMOS acts as Logic 0

NMOS acts as Logic 1

When MOSFET is OFF, it can be modeled as an open switch

When MOSFET is ON, it can be modeled as a Resistor with switch closed

PMOS acts as Logic 0

NMOS acts as Logic 1

When MOSFET is OFF, it can be modeled as an open switch

PMOS

PMOS acts as Logic 1

NMOS

NMOS acts as Logic 0

Vdd

Out

In

Vss

Input Switching from logic 1 to logic 0

Vdd

Out

In

Vss

Input Switching from logic 1 to logic 0

NMOS is turning OFF

Vdd

Out

In

Vss

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON

Input Switching from logic 1 to logic 0

Input Switching from logic 1 to logic 0

NMOS is turning OFF

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON
Vdd

Out

In

Vss

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON
Vdd

Vdd

R
Out

Out

In

Vss

Vss

Replace PMOS as resistor and NMOS by open switch.

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON
Vdd

Vdd

R
Out

Out

CL

Vss
Connect Capacitor on output end.

Vss

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON
Vdd

R
Out

CL

Vss
Consider Capacitor is charged when Vdd is applied.

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON
Vdd

R
Out

CL

Vss
Consider Capacitor is charged up to Vdd

Input Switching from logic 1 to logic 0

NMOS is turning OFF
PMOS is turning ON
Vdd

R
Out

CL

Vss

Summary

Vdd

Vdd

Out

In

Out
CL

Vss

Vss

Summary

Vdd

Out
CL

Vss

Lets convert the area within dotted lines into closed loop circuit.

Summary

Vdd

Out
Vdd

CL
CL

Vss

Lets convert into closed loop circuit.

Summary

Vdd

Out
Vdd

CL
CL

Vss

Lets convert into closed loop circuit.

Summary

Capacitor Models
R

Vdd

CL

Summary

Capacitor Models
R

Vdd

Uncharged Cap

+
0V
-

short

Charged Cap

+
V
- O

+
VO
-

CL

Fully Charged Cap

+
Open circuit
-

Summary

Waveforms

Vdd

CL

Summary

Waveforms

Vdd
R

Vdd

CL

Summary

Waveforms

Vdd
R
VCL
Vdd

CL

Summary

Waveforms

Vdd
R
VCL
Vdd

CL
VR

Summary

Waveforms

Vdd
R
VCL
Vdd

CL
VR

I = V/R

Summary

Waveforms

Vdd
R
VCL
Vdd

CL
VR

I = V/R
IR

Summary

Waveforms

Vdd
R
VCL
Vdd

CL
VR

I = V/R

Ipeak
IR

So what can we conclude!!!

So what can we conclude!!!

A capacitor needs at least Ipeak amount of current

So what can we conclude!!!

A capacitor needs at least Ipeak amount of current
Ipeak
IR

So what can we conclude!!!

A capacitor needs at least Ipeak amount of current
Ipeak
IR

To get charged upto Vdd voltage

So what can we conclude!!!

A capacitor needs at least Ipeak amount of current
Ipeak
IR

To get charged upto Vdd voltage

VCL

So what can we conclude!!!

A capacitor needs at least Ipeak amount of current
Ipeak
IR

To get charged upto Vdd voltage

VCL
And, the output of inverter, is recognized as logic 1

So what can we conclude!!!

A capacitor needs at least Ipeak amount of current
Ipeak
IR

To get charged upto Vdd voltage

VCL
And, the output of inverter, is recognized as logic 1

And, the output of inverter, is recognized as logic 1

And, the output of inverter, is recognised as logic 1

What does this mean????

And, the output of inverter, is recognised as logic 1

What does this mean????

It means that the voltage across capacitor
Vpeak

VCL

And, the output of inverter, is recognised as logic 1

What does this mean????

It means that the voltage across capacitor
Vpeak

VCL

Lies in NMH level of noise margin graph

Vdd
VOH

NMH
Noise Margin High

VIH

NMH = VOH - VIH

NML = VIL - VOL
VIL

NML
Noise Margin High

VOL
0

Why to do?

12/16/2014

65