Digital System Design

Course Introduction
and
VHDL Fundamentals

(Lecture #1)

Course Introduction
(see Syllabus)

Expectations

I am expected to:

1. Properly prepare for each lecture.

2. Attend every class.

3. Do my best to teach the material so that the students learn and
understand it.
4. Be available during office hours and other scheduled meeting times
to answer questions.

You are expected to:

1. Attend class.

2. Spend a minimum of 9 hours each week outside of class learning the

material.
3. Read the text book.
4. Do the homework.
5. Attend the lab and complete all of the lab experiments.

The Design Process

Design conception

9
DESIGN ENTRY
Schematic capture

VHDL

Synthesis

Functional simulation

No

Design correct?
Yes

Physical design

Timing simulation

No

Timing requirements met?

Chip configuration

10

VHDL Fundamentals

Introduction to VHDL
11

What is VHDL?

Very High Speed Integrated Circuit (VHSIC)

Hardware

Description

Language

VHDL: a formal language for specifying the behavior and structure of

a digital circuit.
Note: there are hardware description languages other than VHDL,
namely Verilog.

Basic VHDL Convention

12

VHDL is case insensitive

Naming and Labeling

All names should start with a letter

Should contain only alphanumeric characters, and the

underscore; no other characters allowed

Should not have two consecutive underscores

Should not end with an underscore

All names and labels in a given entity and architecture must be

unique

Basic VHDL Convention

13

Free format language

i.e. allows spacing for readability

Comments start with -- and end at end of line

Use one file per entity

File names and entity names should match

Logic Circuits in VHDL

14

VHDL description includes two parts

Entity statement

Architecture statement

Describes the interface (i.e. inputs and outputs)

Entity
Architecture

Describes the circuit implementation

The Entity Statement

15

Keyword: Entity

Requires a name

Specifies the input and output ports

Ports have

Name

Mode

Data type

Ports: Mode
16

IN

Driver outside
entity

Can be read

OUT

Driver inside
entity
Cannot be
read

INOUT

Driver inside
and outside
entity

Can be read

BUFFER

Driver inside
entity

Can be read

The Architecture Statement

17

Keyword: Architecture

Requires a name

The model is typically chosen as the name

References the name in the associated Entity

Specifies the functionality of the Entity

Using one of several types of implementations

Architecture is associated with an entity

There can be multiple architectures for one entity, but only one
can associated at a time.

The Architecture Statement

18

VHDL Architecture Models

Functional

Logic Functions

Behavioral Includes Timing Information

Structural

Includes Components and Wires

Physical

Specifies Package Information

Each model can be used to describe the functionality of a logic

circuit.
Models are not mutually exclusive.

VHDL: Signals
19

Can be wires or buses (groups of wires)

Wire

STD_LOGIC;

Bus (with 8 wires)

SIGNAL a:
SIGNAL b8:

STD_LOGIC_VECTOR(7 DOWNTO 0);

Bus (with 16 wires)

SIGNAL b16: STD_LOGIC_VECTOR(15 DOWNTO 0);

Can be used to connect entities

Used in the structural architecture model

VHDL Example
20

Architecture
x1
x2
f

x3

Entity

VHDL Example
21

name
mode

ENTITY example1 IS
PORT ( x1, x2, x3 : IN
BIT ;
f
: OUT BIT ) ;
END example1 ;
data type

VHDL Example
22

Architecture name

Entity name

ARCHITECTURE LogicFunc OF example1 IS

BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3) ;
END LogicFunc ;
Boolean expression