Microprocessors and Microcontrollers

Unit 2
Formative Assessment
Ashesh B Vignesh
110110013
I.C.E. Department
2010 2014 Batch

Memory Classification
Can be classified into two groups
Prime (system or main memory)
Storage

R/WM and ROM are examples of Prime memory

Magnetic disks and tapes are examples of storage

memory

Memory Classification

Storage
This memory is used to store programs and result

after the completion of program execution

Information stored in these memories are non
volatile
Information remains intact post system being turned
off
Programs cannot be executed directly from the
storage
Programs must be copied to R/W memory first

Storage
Two main groups of storage memory
Secondary storage
Backup storage

Secondary storage is similar to what one puts in their

shelf
Back up storage is similar to what one puts in their
attic/basement
Primary feature of these devices are:
High capacity
Low cost
Slow access

Prime memory
Prime memory is memory used in executing and

storing of programs
This memory should be able to respond fast
Fast enough to keep up with execution speed of
microprocessor
The microprocessor should be able to access info from
and register with same speed
Can be divided into
Read/Write Memory (R/WM)
Read Only Memory (ROM)

R/WM
Primarily used for information that is likely to be

altered
Information such as writing programs or receiving
data
The memory in R/WM is volatile
Contents are destroyed once power is turned off

Two types of R/W memories exist

Static

Dynamic

Static Memory
Static Ram is also known as SRAM

This memory is made up of flip flops

Stores the bit as a voltage
Each memory cell requires six transistors
Memory chip has low density but high speed
This memory is more expensive and consumes more

power than Dynamic memory

In high speed processors, SRAM also known as cache
memory

Dynamic Memory
Dynamic memory is also known as DRAM

This memory is made up of MOS transistor gates

It stores the bit as a charge
Advantages of DRAM are that it has high density, low

power consumption and is cheaper than SRAM

Disadvantage is that the charge leaks
Stored information hence needs to be read and
written every few milliseconds
This is known as refreshing the memory, and needs
extra circuitry

ROM
The ROM is a non volatile memory
Stores information even if power is turned off

Memory is used for programs and data that does not

need to be altered
As name suggests, information is Read Only
This means that once bit pattern is stored, it is
permanent or semi permanent
Hence there are two types of groups
Permanent
Masked ROM and PROM
Semi permanent
EPROM, EE PROM and Flash Memory

ROM

ROM
The concept underlying ROM has been shown in

matrix format in figure

The horizontal lines are connected to vertical lines
ONLY through diodes
Each of eight horizontal rows can be viewed as a
register with binary address between 000 111
Presence of diode indicates 1, absence indicates 0
When register is selected the voltage of that line goes
high, and the output lines, where diodes are
connected, go high
Example, when 111 is selected, output is 0111 1000

Masked ROM
Bit pattern is permanently recorded by the masking

and metallization process

Memory manufacturers are generally equipped to do
this process
It is an expensive and specialized process, but
economical for large production quantities

PROM
Programmable Read Only Memory

This memory has nichrome or polysilicon wires

arranged in a matrix
These wires can be functionally viewed as diodes or
fuses
Can be programmed with a PROM programmer that
burns the fuses to the bit pattern to be stored
Process is known as Burning the PROM and
information stored is permanent

EPROM
Erasable Programmable Read Only Memory

This memory stores a bit by charging the floating gate

of an FET
Information is stored by using an EPROM programmer
which applies high voltages to charge the gate
All information is erased by exposing chip to
ultraviolet light through its quartz window
This chip can this be reprogrammed
Hence, it is suited for product development,
experimental projects etc.

EE PROM
Electrically Erasable Programmable Read Only

Memory
Functionally similar to EPROM
Difference is that information can be altered by using
electrical signals at register
Hence, no need to erase all information
This memory also includes a Chip Erase mode where
entire chip is erased in 10 m.s.
This memory however is expensive compared to
EPROM

Flash Memory
Popular variation of EE PROM

Major difference between Flash memory and EE

PROM is the erasure procedure

EE PROM is erased at register level, flash memory is
erased in entirety or sector level
The memory chips can be erased and programmed at
least a million times
This memory is ideally suited for low power systems
Power requirement used to be 12 V but is now only 1.8 V

The 8254 Programmable Interval Timer

It generates accurate time delay and can be used for

applications such as
Real time clock
Even Counter
Digital one shot

Square wave generator

Complex wave form generator

8254 includes three identical 16 bit counters

They can operate independently in in any one of the

six modes

The 8254 Programmable Interval Timer

It is packaged in a 24 pin DIP and requires a single +5

V power supply
To operate counter, a 16 bit count is loaded in its
register and, on command, begins to decrement the
count until it reaches 0
At end of count, it generates a pulse that can be used
to interrupt the MPU
The counter can count either in binary or BCD
In addition, count can be read by MPU while counter
is decrementing

Pin configuration of 8254

Pin names of 8254

Block diagram of 8254

Block diagram of 8254

Figures previously show diagrams of 8254

It includes:
Three counters (0, 1 and 2)
A data bus buffer
Read/Write control logic
A control register

Each counter has two input signals

Clock (CLK)

GATE

And one output signal

OUT

Data bus buffer

This tri state, 8 bit, bidirectional buffer is connected

to the data bus of the MPU

Control Logic
Control section has five signals
Read
Write
Chip select
A0

A1

In the peripheral I/O mode, and are

connected to and
In memory mapped I/O, these are connected to
(Memory Read) and (Memory Write)

Control Logic
Address lines A0 and A1 of the MPU are usually

connected to lines A0 and A1 of the 8254

is tied to a decoded address
The control word register and counter are selected
according to the signals on lines A0 and A1 as shown

Control Word Register

This register is accessed when lines A0 and A1 are at

logic 1
It is used to write a command word
This command word specifies the counter to be used,
its mode and either Read or Write operation
This is illustrated in next slide

Control Word Format

The 8255A Programmable Peripheral

Interface
8255A is a widely used, programmable, parallel I/O

device
Can be programmed to transfer data under various
conditions, from simple I/O to interrupt I/O
Flexible, versatile and economical, but somewhat
complex
It is an important general purpose I/O device that
can be used with almost any microprocessor

The 8255A Programmable Peripheral

Interface
The 8255A has 24 I/O pins that can be grouped

primarily in two 8 bit parallel ports: A and B

The remaining eight bits are grouped as Port C
The eight bits of Port C can be used as individual bits
or be grouped in two 4 bit ports
CUPPER (CU) and CLOWER (CL) as show in the I/O ports figure

a)
The b) of the figure in next slide shows all functions of

8255A, classified according to two modes

The Bit Set/Reset (BSR) mode
The I/O mode

8255A I/O ports and their modes

The 8255A Programmable Peripheral

Interface
The BSR mode is used to set or reset the bits in port C
The I/O mode is further divided into three modes:

Mode 0, Mode 1, Mode 2

In Mode 0, all ports function as simple I/O ports
Mode 1 is a handshake mode whereby ports A and/or
B use bits from port C as handshake signals
In handshake mode, two types of I/O data transfer can
be implemented
Status check and Interrupt

In mode 2, Port A can be set up for bidirectional data

transfer using handshake signals from port C

Port B can be set up either in Mode 0 or Mode 1

Pin Configuration of 8255A

Block Diagram of 8255A

Block diagram of 8255A

The block diagram shows
Two 8 bit ports (A and B)
Two 4 bit ports (CU and CL)
The data bus buffer
Control logic

The block diagram includes all the elements of a

programmable device
Port C performs functions similar to that of the status

register in addition to providing handshake signals

Expanded version of control logic and

I/O ports

Control Logic
The control section has six lines

(Read)
This control signal enables read operation
When signal is low, the MPU reads data from a selected

I/O port of the 8255A

(Write)
This control signal enables the Write operation
When the signal goes low, the MPU writes into a

selected I/O port or the control register

RESET
This is an active high signal it clears the control register

and sets all ports in the input mode

Control Logic
, A0 and A1
These are device select signals
is connected to a decoded address
A0 and A1 are generally connected to MPU address lines

A0 and A1
The signals is the master Chip Select
A0 and A1 specify one of the I/O ports as given below

Control Word
The control logic figure shows a register called control

register
Contents of this register are called the control word
They specify an I/O function for each port

This register can be accessed to write a control word

when A0 and A1 are at logic 1

This register is not accessible for a Read operation

Control Word
Bit D7 of the control register specifies either the I/O

function or the Bit Set/Reset function

If bit D7 = 1, bits D6 to D0 determine I/O functions in
various modes
If bit D7 = 0, port C operates in Bit Set/Reset (BSR)
mode
The BSR control word does not affect the functions of
ports A and B

Control Word
To communicate with peripherals through the 8255A,

three steps are necessary

Determine the addresses of ports A, B and C and of the
control register, according to Chip Select logic and
address lines A0 and A1
2. Write a control word in the control register
3. Write I/O instructions to communicate with
peripherals through ports A, B and C
1.

Timing Diagrams
Definition
A timing diagram is a representation of a set of signals in

the time domain.

A timing diagram can contain many rows, usually one

of them being the clock

It is a graphical representation
Represents the execution time of an instruction in a
graphical format
The execution time is represented in T states

Timing Diagrams
T state
The machine cycle and instruction cycle takes multiple

clock periods.
A portion of an operation carried out in one system clock
period is called as T-state
Instruction cycle
The time required to execute an instruction is called

instruction cycle
Machine cycle
The time required to access the memory or

input/output devices is called machine cycle

Timing Diagrams

Machine cycle of 8085

The 8085 has 3 important machine cycles
Opcode Fetch cycle
Memory Read Cycle
Memory Write Cycle

Each instruction of the 8085 processor consists of one

to five machine cycles

When the 8085 processor executes an instruction, it
will execute the machine cycles in a specific order
The processor takes a definite time to execute the
machine cycles

Machine cycle of 8085

The time taken by the processor to execute a machine

cycle is expressed in T-states

One T-state is equal to the time period of the internal
clock signal of the processor
The T-state starts at the falling edge of a clock

Opcode Fetch Machine Cycle

The first step to executing any instruction is the

Opcode fetch cycle

Each instruction of the processor has one a byte
opcode
The opcodes are stored in memory
Processor executes the opcode fetch machine cycle to
fetch the opcode from memory
Hence, every instruction starts with opcode fetch
machine cycle

Opcode Fetch Machine Cycle

The control and status signals are set as follows:
/ = 0, 1 = 1, 0 = 1
This machine cycle uses up four T states

The first 3 T- states are used to fetch the opcode

The 4th T state is used to decode and execute it
At certain times, it is possible for an instruction to

have 6 T states in an opcode fetch machine cycle

Opcode Fetch Machine Cycle

Opcode Fetch Machine Cycle

T1 State
During the T1 state, the contents of the program counter are

placed on the 16 bit address bus

The higher order 8 bits are transferred to address bus (A8-A15)
Lower order 8 bits are transferred to multiplexed A/D (AD0AD7) bus
After the address bits are transferred, the ALE (address latch
enable) signal goes high
As soon as ALE goes high, the memory latches the AD0-AD7
bus
At the middle of the T state the ALE goes low
The complete 16-bit address is made available for the Opcode
fetch machine cycle

Opcode Fetch Machine Cycle

T2 State

During the beginning of this state, the signal goes low to

enable memory
It is during this state, the selected memory location is placed
on D0-D7 of the Address/Data multiplexed bus
T3 State
In the previous state the Opcode is placed in D0-D7 of the A/D

bus
In this state of the cycle, the Opcode of the A/D bus is
transferred to the instruction register of the microprocessor
Now the goes high after this action and thus disables the
memory from A/D bus
T4 State

In this state the Opcode which was fetched from the memory

is decoded

Memory Read Machine Cycle

The memory read machine cycle is executed by the

processor to read a data byte from memory

This is exactly the same as the opcode fetch cycle
However, the processor takes 3T states to execute this
cycle
Also, we have the control and status signals as:
/ = 0, 1 = 1, 0 = 0
Instructions which have 2 or more word size will use the

machine cycle after the opcode fetch cycle

Memory Read Machine Cycle

To understand the difference between memory read

and opcode fetch:

Consider any 2 byte instruction, for example MVI A, 32
The first byte represents the opcode for loading byte
into accumulator (MVI A)
Second byte is the data to be loaded (32)
Microprocessor needs to read 2 bytes from memory
before it can execute instruction
It will need at least 2 machine cycles:
First will be opcode fetch
Second will be memory read

Memory Read Machine Cycle

Memory Read Machine Cycle

T1 state
In this state the contents of the program counter is

placed on the higher order address bus (A8-A15)

Lower order address and data multiplexed (AD0-AD7) bus
ALE goes high so that the memory latches the (AD0-AD7)
Then during the middle of the T1 state ALE goes low, so
that complete 16-bit address are available
The microprocessor then identifies the memory read
machine cycle from the status signals / = 0, 1 =
1, 0 = 0
This condition indicates the memory read cycle

Memory Read Machine Cycle

T2 state
Selected memory location is placed on the (D0-D7) of the

A/D multiplexed bus

T3 State
The data which was loaded on the previous state is

transferred to the microprocessor

In the middle of the T3 state goes high and disables
the memory read operation
The data which was obtained from the memory is then
decoded

Memory Write Machine Cycle

The memory write machine cycle is executed by the

processor to write a data byte in a memory location

The processor takes, 3 T states to execute this
machine cycle
The 8085 places the address on the address bus
Identifies the operation as a memory write
The control and status signals are
/ = 0, 1 = 0, 0 = 1
Places the contents of the accumulator on the data bus

and asserts the signal .

During the last T state, the contents of the data bus

are saved into the memory location

Memory Write Machine Cycle

Memory Write Machine Cycle

T1 State
This is Opcode fetch
The 16 bit address is placed on the higher order address

bus (A8-A15) and lower order A/D bus (AD0-AD7)

The ALE goes high to latch the AD0-AD7 bus and during
the middle of T1 state it goes low
This is so that the complete 16 bit address is available
The processor can recognize the operation using control
and status signals
For memory write cycle the values of status signals
should be / = 0, 1 = 0, 0 = 1
This status information is always maintained throughout
the machine cycle

Memory Write Machine Cycle

T2 State

At the beginning of this state goes low

Unlike in the read cycle the goes low to enable

memory
During this state the contents of the register is placed on
the Data bus
T3 State
The data placed on the data bus in the previous state is

now transferred to the specific memory location

In the middle of this state the goes high and
disables the memory
Thus the data is transferred from the accumulator to
specific memory location
This is the memory write machine cycle

Memory Interfacing
Primary function of memory interfacing
The processor should be able to read from and write

into a given register of a memory chip

To perform such an operation, microprocessor should:
Be able to select the chip

Identify the register

Enable the appropriate bugger

We shall examine memory read operation to

understand how 8085 reads form a memory chip

The memory chip used is shown in figure in next slide

a) R/W Static Memory b) EPROM

Memory Interfacing
The 8085 places a 16 bit address on the address bus
Only one register is to be selected with this address

For the memory chip shown in previous slide, only 11

address lines are required to identify 2048 registers

Therefore, we can connect low order address lines
A10 A0 of address bus to memory chip
Internal decoder of the memory chip will identify and
select the register for the EPROM
A15 A11 should be decoded to generate Chip Select
() unique to that combination of address logic

Memory Interfacing
The 8085 provides two signals / and to

indicate it is a memory read operation

The / and can be combined to generate
that can be used to enable output buffer
Done by connecting to the memory signal

To write into a register, the microprocessor performs

similar steps
In write operation, it places the address and data and
asserts the / signal
After allowing sufficient time for the data to become
stable, it asserts the signal

Memory Interfacing
The / and signals can be combined to

generate

This enables the input buffer of memory chip and stores

the byte in the selected memory register

Memory Interfacing Summary

We can summarize memory interfacing as follows:
Connect the required address lines of the address bus to

the address lines of the memory chip

Decode the remaining address lines of the address bus
to generate the Chip Select signals
Connect the signal to select chip
Generate control signals and
Combine , signals with IO/

Use them to enable appropriate buffers