CSE 242A Integrated

Circuit Layout Automation

Lecture: Floorplanning
Winter 2009
Chung-Kuan Cheng

Outlines

Introduction
Representations and Approaches

Constraint Graph
Triangulation
Tuttes Duality
Slicing Flooplanning
Nonslicing ...

Block Handling
Research Directions

Introduction

Input
A set of blocks with constraints on
area, shapes, relative positions,
Constraints on chip area and aspect ratio,
Netlist.
Output
Shapes, Locations, Pin positions of the
blocks
Objective Functions
Performance, chip area, and wire length

Representations
Constraint Graph
Theorem: A V or H constraint graph is planar
and acyclic.
d ij
i

dij
i

horizontal edge
x j xi dij
vertical edge
y j yi dij

Constraint Graph Generation

# Edges O(n2), O(n)

Constraint Graph Generation

Scan from left to right at cur_x;
Update scaline: list of blocks crossing scanline.
For blocks T strating at cur_x;
Insert T into scanline list
R->T->S
Generate edges
R->T and T->S
End

Constraint Graph Generation 2

Scan from left to right at cur_x;
Update scanline: list of blocks crossing scanline.
For blocks T starting at cur_x;
Insert T into scanline list: R->T->S
Generate list:T.top=R, R.bot=T, T.bot=S, S.top=T
End
For block T ending at cur_x;
if T.top is list in scanline, generate edge T.top->T;
if T.bot is list in scanline, generate edge T->T.bot
End
End

Floorplan Triangulation

Floorplan with dead space

Floorplan with zero dead space

Triangulation

For floorplan with zero dead space, H & V

constraint graphs are dual.

H&V
Every face is a triangle
All internal nodes have a degree >= 4
All cycles that are not faces have length >= 4

Triangulation 2

Node oriented vs edge oriented constraint graph

8

c
e

3
d

4
5
6

g
7

10

Tuttes Duality

s
c
a

c
a
d

b
b
d
t

Slicing Floorplan & General

Flow
V
H

H
2

V
1

5
4

Nonslicing

Routing Region Definition &

Ordering

Straight Channel

1
a

L Shaped

3
2

Non-Feasible Order

b
a

1
c

c
Feasible Order

Polish Expression
v
3

4
H
2

7
2

V
1

21H57V43H6VHV

H
7

Given n components, there are n-1 operators

Polish Exp has 2n-1 length

Polish Exp is legal iff

# operators <= # comps 1
For any prefix substring
2 1 H5 7 V 4 3 H 6 V H V
215H7V43H6VHV
215HVHV7436HV

Redundancy of Polish Exp

1

V
V

V
V
1
1

12V3V

3
123VV

No consecutive operators of the same type

Neighborhood Structure

OP. Chain: VHVHV or HVHV

23V14H5V6HVV
M1: Swap adjacent components
M2: Complement a chain
M3: Move an operator under the prefix
constraint of # operators <= # comps 1

5
3

1 2 V 3 H4 V 5 H
1

2
5

5
4

12V4H3V5H

3
1

12H435HVH

5
12H435VHV
2

5
3
2
1

3
4

12V4H35VH

12V43H5VH

12V435HVH

5
4

The choices of macro cell

H
3
4

2
H
1
1
Hi

2
Hj

H ij ( w) H i ( w) H j ( w)

Hierarchy Floorplan
K=2

K=3

K=4

b
d

c
e
a1

a3
a4

a2 a5 a6

a11
a12
a13

a14

b1
b3 b4

b2
b5

Sequence Pair
1 ab ba ab ba
2 ab ab ba ba
b

Eg. c a e b d

abcde
c

e
#combinations

(n !) 2

Grid System Interpretation

5

c
x

a
1

l
3

Bounded-Sliceline Grid

Perturbation: move a component to another

room

BSG Adjacency Graphs

Theorem: nxn grid contains the complete

solution space for n components

Twin Binary Trees

Definition of Twin Binary Trees
Transformations between Floorplan and
Twin Binary Trees

900

00

C+-neighbor: 00 T-junction, block on right

2700 T-junction, block on top
B
00

C--neighbor: 900 T-junction, block on top

1800 T-junction, block on left
A
900
B

B
1800

Twin Binary Trees

1800

2700

2700

Twin Binary Trees

F

C
E

A
D
F

D 0 X

X X

E
X

(1)=11001

0
0

(2)=00110
order(1)=order(2)=ABCDFE

Twin Binary Trees and Mosaic Floorplan

Twin Binary Tree Mosaic Floorplan
: one to one mapping
Transformation between twin binary trees and
mosaic floorplan takes linear complexity
#twin binary trees = Baxter number

Corner Block List

Corner Block List Mosaic Floorplan
A permutation and two 0-1 lists
e.g. S=(fcegbad), L=(001100), T=(001010010)

Corner Block List

S=(fcegbad), L=(001100),
T=(001010010)
S is the reversed sequence of removed
blocks
L[i] is the removing direction of block i
Number of 0s before ith 1 in T is the
number of blocks covered by S[i] when it is
removed

Corner Block List

Redundancy (L and T are not independent)

Solution space size O(n!23n-3/n1.5)
Can be reduced to O(n!23n-3/n4), no
redundancy

Floorplan Optimization Flow

Simulated annealing (SA) in the

representation solution space

s := s0; e := E(s)
sb := s; eb := e
k := 0
while k < kmax and e > emax
sn := neighbour(s)
en := E(sn)
if en < eb then
sb := sn; eb := en
if P(e, en, temp(k/kmax)) > random() then
s := sn; e := en
k := k + 1
return sb

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Initial state, energy.

Initial "best" solution
Energy evaluation count.
While time remains & not good enough:
Pick some neighbour.
Compute its energy.
Is this a new best?
Yes, save it.
Should we move to it?
Yes, change state.
One more evaluation done
Return the

E() is the objective function

neighbour(s) comes from perturbation on s