TechInsights Technology Roadmap INTEL Processors 2014

Technology Roadmap
of
INTELs Processors
July 2014
Table of Contents
Intels product line from Pentium to Ivy Bridge
Above 100 nm node (Gate-First)
Sub-100 nm nodes:
90 nm and 65 nm (Gate-First)
45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)
Parameters related to Technology Node
Contacted Gate Pitch
6T SRAM Cell Size
Metal 1 Pitch
Future
What to expect NEXT?
Technology Roadmap Intel Processors 2014
Content for re-use only with TechInsights
Above 100 nm, Gate-First:
Package (top & bottom)
0.35 m
0.18 m
Intel Pentium
Intel III Microprocessor
Microprocessor (200 MHz) Coppermine (450 MHz)
0.13 m
Tualatin (1.26 GHz)
Above 100 nm, Gate-First: Die and Die markings

0.35 m
Intel Pentium
Microprocessor (200 MHz)
0.18 m
Coppermine (450 MHz)
0.13 m
Tualatin (1.26 GHz)
7.1 mm x 11.1 mm = 79 mm2

10.8 mm x 12.6 mm = 136.1 mm2
10.3 mm x 12.3 mm = 126.7 mm2
Above 100 nm, Gate-First: SRAM at gate level

0.35 m
Intel Pentium
Microprocessor (200 MHz)
0.18 m
Coppermine (450 MHz)
0.13 m
Tualatin (1.26 GHz)
All the SRAMS: P+ diffusions of the pull-down transistors have an H shape and
each one is shared by two SRAM cells
Wordline and pull-down are 90 at each other and this consumes lot of space
Above 100 nm: Critical Parameters

Parameters
0.35 m Node
Die size
NMOS gate length
PMOS gate length
Minimum metal 1
pitch
Gate oxide thickness
Contacted gate pitch
Silicide
Metallization levels
SRAM cell size
136 mm2
335 nm
330 nm
0.18 m
0.13 m Node
Node
126.7 mm2
79 mm2
120 nm
70 nm
130 nm
70 nm
950 nm
750 nm
360 nm
5 nm
1480 nm
TiSi
4 (A1)
18.1 m2
2.5 nm
760 nm
CoSi
6 (A1)
6 m2
1.9 nm
510 nm
CoSi
6 (Cu)
3.25 m2
The devices before 0.35 m are not taken because previous two
generations (0.6 m and 0.8 m) used BiCMOS process
The 0.25 m node has been omitted to avoid clutter
Above 100 nm: Summary

In four generations (0.35 m, 0.25 m, 0.18 m, 0.13 m):
The die area shrunk from 136 to 79 mm2
The gate length reduced from 335 nm to 70 nm
The metal 1 pitch scaled down from 950 nm to 360 nm
The SRAM cell size decreased from 18.1 m2 to 3.25 m2
Not all parameters scaled in the same proportion
Intel moved towards sub 100 nm nodes with process-integration
experience in
Cu-interconnects and low-k materials
By 130 nm node all the processors had a clock frequency in the range of 3
GHz
Sub 100 nm, Gate-First:
Package
(Top & Bottom)

90 nm
Intel Pentium IV,
Prescott
(3 GHz)
65 nm
Intel Dual Core,
Xeon
(3 GHz)
90 nm and 65 nm are two
generations below 100 nm
nodes, which used
conventional gate structure
with poly for gate electrode
and oxide for gate dielectric
65 nm node was essentially a
shrink of 90 nm
The most innovative part in 65
nm node was the introduction
of dual core architecture

markings
90 nm
Intel Pentium IV,
Prescott
(3 GHz)
10.8 mm x 10.34 mm
= 112 mm2
Die and Die

65 nm
Intel Dual Core, Xeon
(3 GHz)
13.4 mm x 10.4 mm =
142 mm2

level
90 nm
Intel Pentium IV,
Prescott
(3 GHz)
SRAM at gate
65 nm
Intel Dual Core, Xeon
(3 GHz)
The SRAM cell at diffusion changed from H_O structure to continuous

regions of P-well for NMOS transistors and I shaped regions of N-well
for PMOS transistors
Intel 65 nm node is 2nd generation of strain silicon technology
65 nm node adopted the same uniaxial strained approach as 90 nm
node
Epitaxial SiGe film was employed for PMOS source-drains in 65 nm
and Roadmap
90 nmIntel
node
Technology
Processors 2014
10
Sub 100 nm, Gate-Last:
Package
(Top & Bottom)

45 nm
Intel Core 2TM Extreme,
Penryn (3 GHz)
32 nm Intel Dual
Core,
Clarkdale/Westmer
e
(3 GHz)
22 nm
Intel Quadcore, Ivy
Bridge
(3.3 GHz)
11
Die and Die
Markings
45 nm
Penryn (3 GHz)
32 nm Intel Dual
Core,
Clarkdale/Westmer
e
(3 GHz)
22 nm
Intel Quadcore, Ivy
Bridge
(3.3 GHz)
12.2 mm x 8.5 mm =
104 mm2
9.2 mm x 8.2 mm =
75.4 mm2
19.6 mm x 8.0 mm
=
112 mm2
12
SRAM at
gate level
45 nm
Penryn (3 GHz)
32 nm Intel Dual
Core,
Clarkdale/Westmer
e
(3 GHz)
22 nm
Intel Quadcore, Ivy
Bridge
(3.3 GHz)
The 6T SRAM cell has been the vehicle to define technology nodes
Cross couple PMOS and NMOS metal gates are connected at the side of the
metal gate.
45 nm node uses double patterning with 193 nm dry lithography
32 nm node uses double patterning with 193 nm immersion lithography
22 nm node introduces fins and uses double patterning with 193 nm immersion
lithography
13
Summary
Intels 45 nm process is the first to incorporate high-k metal gate (HKMG)

technology. Their innovative process protects the high-k gate dielectric from
polysilicon etch by depositing a TiN top interface layer (TIL) before polysilicon
deposition and patterning.
PMOS channel stress is enhanced by removing the polysilicon dummy gates
which is an enabling factor of the replacement metal gate process Intel used for
the first time double patterning based on 193 nm dry lithography for critical
layers and at the transistor gate level. Intels 32 nm was essentially a shrink of
45 nm node with the exception that immersion lithography was used.
As of today, 2014, Intel is the only manufacturer to use a FinFET for its
transistors. Intel 22 nm replaced the traditional 2-D planar MOS transistor
with a gate that is wrapped around a thin three-dimensional silicon fin that rises
up vertically from the silicon substrate . A thin high-k dielectric separates the
silicon fin from the metal gate on each of the three sides of the fin
14
Graphical
Summary
15
Sub 100 nm:

Node
Lithography
Process
Critical Dimensions (Logic)
90 nm
248 nm dry
65 nm
193 nm dry
45 nm
32 nm
22 nm
193 nm dry
193 nm
immersion +
double
patterning
193 nm
immersion +
double
patterning
Tri-gate
SiGe is used to
SiGe_PMOS;
transistor;
strain a silicon
SiGe for PMOS;
eSi_NMOS;
SiGe for PMOS;
SiG3_PMOS;
channel;
Metal gates
Metal gates
Poly gates; W
eSi_NMOS;
tensile nitride
with High-K; W with high-K,
contact, M1 in
Metal gates,
layer for NMOS
contact; M1 in M0 level in Cu;
Cu
M0 level in W;
channel; Ni-Si
Cu
W contact; M1
W contact; M1
replaces Co-Si
in Cu
in Cu
Minimum
Contacted Gate
Pitch (nm)
310
220
160
113
90
Minimum Gate
Length (nm)
45
36
45
34
25
Minimum Metal
1 Pitch (nm)
220
210
150
113
90
90 nm and 45 nm have the same gate-length

65 nm and 32 nm have the same gate-length
Gate length is not an accurate parameter for defining technology node for
devices below 100 nm node
16
Sub 100 nm:
Critical Dimensions (SRAM)
The 32 nm node introduced the metal 0 level and changed the wiring position of bitlines
(BL),
Wordlines (WL), Vss and Vdd lines and improved slightly the width/length (W/L) ratio of
transistors
The SRAM in 22 nm node kept the same wiring configuration for BL, WL, Vdd and Vss, as
in 32 nm node but by introducing Tri-Gate (FinFET) structure improved W/L ratio
Generally, the widths of pull down transistors are greater than the widths of access
transistors. The current ratio of I PD /I AC reflecting geometric device dimension is known
Technology
Roadmap
Processors
Content for
re-use only
TechInsights
as
beta ratio.
A Intel
higher
beta2014
ratio reflects
higher
cellwith
stability
17
Table of Contents
Sub-100 nm nodes:

6T SRAM Cell Size
Metal 1 Pitch
Future
18
Parameters related to Technology

Node
For advanced nodes Gate-Length is not a reliable parameter for defining

technology node
19

Node
The Contacted Gate Pitch takes in account the gate length and the
minimum litho-features, thus reflects the actual technology node
Contacted Gate Pitch decreases by 0.7 every two years, following Intels
Tick Tock scheme
Every alternate year Intel develops a new process technology and the
following year a new
Technology
Roadmap Intel Processors(Tick
2014 / Tock
Contentscheme)
for re-use only with TechInsights
micro-architecture,
20

Node
The square root of 6T-SRAM cell area is linear with technology node and is
an accurate method to determine the technology node
Intel 22 nm has 0.092 m2 SRAM cell for high density applications but our
analysis did not locate these cells, only 0.108 m 2 SRAM cell for low voltage
applications was found in reverse engineering.
21

Node
The Metal 1 Pitch is also indicative of the technology node but not very
accurate
22
Table of Contents
Sub-100 nm nodes:

6T SRAM Cell Size
Metal 1 Pitch
Future
23
What is coming NEXT?

Intel has developed both CPU and SoC processes for its 45 nm, 32
nm and 22 nm technology nodes
SoC products usually incorporate a variety of devices that are often
not seen in regular CPU products
Intel will use the 22 nm technology node platform and diversify for
different products
Intel is not pursuing only high performance, but developing process
and architectures for wider range of products varying from servermarket to mobile market
This wide variety of products requires different design at one
particular technology node
24

Different chips with different designs are available at 22 nm
technology, for example:
Ivy Bridge ( CPU);
Haswell (SoC);
Bay Trail (for tablets, Atom Z300 series)
Intel 22 nm
Ivy Bridge
Intel 22 nm
Haswell
Bay Trail 22 nm
ATOM Z300
25

Generation of High-K and Metal Gates with GateLast process
Most likely bulk FinFET will be used for 14 nm node

EUV will probably be used for sub 10 nm nodes
26
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Technology Roadmap

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Above 100 nm, Gate-First:

Package (top & bottom)

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Above 100 nm, Gate-First: Die and Die markings

7.1 mm x 11.1 mm = 79 mm2

Technology Roadmap Intel Processors 2014

10.3 mm x 12.3 mm = 126.7 mm2

Content for re-use only with TechInsights

Above 100 nm, Gate-First: SRAM at gate level

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Above 100 nm: Critical Parameters

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Above 100 nm: Summary

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Sub 100 nm, Gate-First:

(Top & Bottom)

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Sub 100 nm, Gate-First:

Technology Roadmap Intel Processors 2014

Die and Die

Content for re-use only with TechInsights

Sub 100 nm, Gate-First:

The SRAM cell at diffusion changed from H_O structure to continuous

Sub 100 nm, Gate-Last:

(Top & Bottom)

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Sub 100 nm, Gate-Last:

Die and Die

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Sub 100 nm, Gate-Last:

Content for re-use only with TechInsights

Sub 100 nm, Gate-Last:

Intels 45 nm process is the first to incorporate high-k metal gate (HKMG)

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Sub 100 nm, Gate-Last:

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Sub 100 nm:

Critical Dimensions (Logic)

90 nm and 45 nm have the same gate-length

Content for re-use only with TechInsights

Sub 100 nm:

Critical Dimensions (SRAM)

Parameters related to Technology Node

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Parameters related to Technology

For advanced nodes Gate-Length is not a reliable parameter for defining

Technology Roadmap Intel Processors 2014

Content for re-use only with TechInsights

Parameters related to Technology

Parameters related to Technology