THE INVERTER

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

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DIGITAL GATES
Fundamental Parameters
The key parameters that govern a digital
gates performance and usability.

Area and Complexity

Functionality and Robustness
(Reliability)
Performance
Speed (delay)
Power Consumption (dissipation)
Energy

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Area and Complexity

Small area very desirable for digital
gate
higher integration density
smaller die size
lower fabrication cost
faster (smaller Cg)
Implementation area
depends on number of transistors
interconnection area
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Functionality and Robustness

Prime requirement for digital gate:
perform designed function
Measured behavior deviates from expected response.
Why?
variations in process
noise (unwanted variations of voltages and
currents at the logic nodes)
Logic levels
VOH and VOL represent high and low logic levels
difference is called the logic swing
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Noise in Digital Integrated Circuits

v(t)

VDD

i(t)

(a) Inductive coupling

(b) Capacitive coupling

(c) Power and ground

noise

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The Voltage-Transfer
Characteristic
Electrical function of gate is best
expressed by its voltage-transfer
characteristic (VTC)
(DC transfer characteristic)
Plots Vout =f(Vin)
Gate (Switching) logic threshold voltage,
VM:
VM=f(VM)

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DC Operation:
Voltage Transfer Characteristic (VTC)
V(y)

V(x)
f

OH

V(y)=V(x)

Switching Threshold

VOL

VOL

V
OH

V(x)

Nominal Voltage Levels

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V(y)

Mapping between analog and digital

signals
Problem:
Output signal deviates from expected nominal value
due to:
noise
loading of the gate output
Solution:
Logic levels represented by range of acceptable
values
Regions of acceptable values delimited by VIH and
VIL
points in VTC where (dVout/dVin) = -1
represents
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VLSI Design

Mapping between analog and digital

signals

"1"

OH
V
IH

V(y)
Slope = -1

V
OH

Undefined
Region

"0"

V
IL
V
OL

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Slope = -1
VOL
V

IL

IH

V(x)

Noise Margins
Measure of a gate sensitivity to noise
Quantize the size of legal 0 and 1
Represents level of noise that can be tolerated when
gates are cascaded
NML (noise margin low)
NML = VIL - VOL
NMH (noise margin high)
NMH = VOH - VIH
Should be large as possible for good noise immunity
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Definition of Noise Margins

"1"
V

OH

NMH

Noise Margin High

Noise Margin Low
V

NML

V
IH
Undefined
Region
V

IL

OL

"0"
Gate Output

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Gate Input

The Regenerative Property

Large noise margin alone not sufficient for
proper operation
Gate must boost weak levels back to
nominal values
Known as regeneration (of levels)
Non-regenerative gate output will converge
to intermediate value
Conditions for regeneration:
VTC transient region gain >1 (absolute
value)
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Gain in the two legal zones must be < 1

The Regenerative Property

...
v1

v0

v2

v3

v5

v4

v6

(a) A chain of inverters.

v1, v3, ...

v1, v3, ...

finv(v)

f(v)

finv(v)

v0, v2, ...

(b) Regenerative gate

EE415 VLSI Design

f(v)

v0, v2, ...

(c) Non-regenerative gate

Directivity
A gate must be unidirectional:
input not affected by output changes
causes noise in input otherwise
Real gate:
full directivity never achievable
capacitive coupling causes feedback

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Fan-in and Fan-out

Fan-out:
Number of load gates, N, that are connected to
the output of the driving gate
tends to lower the logic levels
deteriorates dynamic performance
gate must have low output resistance to drive
load
library cells have maximum fan-out specification
Fan-in:
Number of inputs, M, to the gate
large fan-in gates are more complex
results in inferior static and dynamic performance
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Fan-in and Fan-out

(a) Fan-out N

M
N

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(b) Fan-in M

The Ideal Gate

Vout

Ri =
Ro = 0
g=
Vin

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Static CMOS comes close to

ideal

VTC of Real Inverter

5.0

Vout (V)

4.0

NML

3.0
2.0

VM

1.0
0.0

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1.0

NMH

2.0
3.0
Vin (V)

4.0

5.0