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Accessing I/O Devices: Processor Memory BUS
Accessing I/O Devices: Processor Memory BUS
Processor
Memory
BUS
I/O Device 1
I/O Device 2
Parallel I/O
I/O devices connect to processor through PORTS
Ports are:
registers (part of the I/O interface)
8, 16, or 32 bits wide
Addressed in the range 0000-FFFFh
Accessed with 2 instructions IN, OUT
AL, 27h
Instruction
Description
Direct
IN AL, port
IN AX, port
IN EAX, port
OUT port, AL
OUT port, AX
OUT port, EAX
IN AL, DX
IN AX, DX
IN EAX, DX
OUT DX, AL
OUT DX, AX
OUT DX, EAX
INSB
INSW
INSD
OUTSB
OUTSW
OUTSD
Indirect
String
Memory Space
16-bit
address
I/O Space
M/IO = 1
M/IO = 0
Memory-Mapped I/O
I/O Devices and memory share the same
address space.
Each I/O Device is assigned a unique set of addresses.
When the processor places a particular address on the
address lines, the device recognizing this address
responds to the commands on the control lines.
The processor requests either a read or a write
operation, and the requested data is transferred over the
data lines.
Any machine instruction that can access memory can
be used to transfer data to/from I/O devices.
Mov datain, R0
Intel Architecture
Intel processors have a separate 16-bit address
bus for I/O devices
Designer has the option of
connecting I/O devices to use special address space
or simply incorporating them as part of the memory
address space.
Programmed I/O
(driving Hardware devices through I/O ports)
External devices are almost always connected not
directly to the system bus but to an INTERFACE.
Registers in the interface allow for a wide range
of possibilities for the designer to determine how
it is to interface to the bus.
TO avoid confusion with the main registers in the
8086, peripheral interface chip registers are
usually referred to as PORTS.
Interface Ports
Typically consists of three registers
Control Port - the setting of which will determine if the
interface is to send or receive.
Data Port for the data element to be transmitted or to
hold a data element received.
Status Port used to obtain information such as
printer out of paper, dont send any more data or, for
a serial transmission, all the bits of the data element
havent yet been received
Simple interfaces may have status and control
combined into one port; sophisticated ports may have
multiple control and status ports.
Address
Decoder
Control
Circuits
Data and
Status Registers
I/O Interface
Input Device
I/O Interfacing
A lot of handshaking is required between
the CPU and most I/O devices.
All I/O devices operate asynchronously
with respect to the CPU. The events that
determine when an input device has data
available or when an output device needs
data are independent of the CPU.
Synchronization
The CPU must have some way of checking
the status of the device and waiting until it
is ready to transfer
Transfer Rate
A measure of the number of bytes per
second transferred between the CPU and an
external device.
Maximum transfer rate a measure of the
bandwidth capability of a particular method
of doing I/O.
Latency
Measure of the delay from the instant that
the device is ready until the time the first
data byte is transferred. Latency is
equivalent to the response time
Comparison of Latency
Polled Waiting Loops latency can be very
high (the computer may not even be
checking the device for new data when it
arrives).
Interrupt-driven I/O dramatically lower
than polled, but still imposes a software
overhead.
DMA very low (lower than the others)