Unit II

Interrupt Structure
Interrupt Vector Table (IVT)
ISR
Hardware and software Interrupts
Internals of DOS
DOS loading
DOS memory map
Internal and external commands of DOS
BIOS & DOS Interrupts
Concepts of PSP, .EXE & .COM files
Concepts of TSR
8259 (Programmable Interrupt Controller): Features,
Block Diagram, Control & status registers, Interfacing &
Programming
Computer Memory & Memory Mapping in 64 Bit

Interrupts
An interrupt refers to the change in
state of the CPU as a result of a
condition which is external to the
system or within the system.
The terms exception, trap, supervisor
call, system call are the synonyms of
the term interrupt.

Intel Definition Of Interrupt

Interrupts and exceptions are special kinds of
control transfer; they work somewhat like
unprogrammed CALLs.
They alter the normal program flow to handle
an external event or to report error or
exceptional condition.
The difference between interrupts and
exception is that the interrupts are used
handle asynchronous events (processor does
not wait for an event to occur ) external to the
processor and exceptions handle conditions
detected by the processor itself in the course of
executing instructions.

 An interrupt is a hardware signal that informs

the CPU to temporarily halt its current
activities and transfer control to a program
called interrupt handler or Interrupt Service
Routine (ISR).
The CPU would have to constantly check for
external events in the absence of interrupts
which is called as Polling; with interrupts , the
CPU can perform some other operation and
still respond to an event as soon as it occurs.

Interrupt vs. Polling

Polling
Ask the device if it has any data
All intelligence is in the CPU
CPU controls interaction with the
device

Interrupts
Device tells the CPU that is ready with/for
data or needs service by interrupting the CPU
Intelligence is moved to the device
Device informs the CPU when it needs
service

Which is better/faster?

3.Interrupts are more complicated

Difficult to debug due to asynchronous behavior
Debugging can alter the behavior of the
interrupt
Transient bugs - debug version works, normal version does not

More setup involved to write ISR

All code called by ISR must be re-entrant, i.e.,
callable while it is already being executed
4.Example of interrupt versus polling
Lecture
Polling asking if there are any questions, students
respond
o 10 students Ask each student
o 100 students Ask each student

Interrupt Students raise hand, instructor calls on

students

 An interrupt is an external event which informs

the CPU that a device needs its service.
There are 256 interrupts (types): INT 00, INT
01,
, INT FF in the 8086.
When executes an interrupt, microprocessor
automatically saves the flag register, the
instruction pointer, and the code segment
register on the stack, and goes to a fixed
memory location.

Classification I
Interrupts can be broadly categorized
into 3 groups:
1.External Hardware Interrupts
2.Internal Hardware Interrupts
3.Software Interrupts (INT
instruction)

1.External Hardware Interrupts :Requests from

peripheral devices for processor action or attention.
It is due to the activity external to the processor.
2.Internal Hardware Interrupts: are the exceptions,
generated internally due to the illegal or invalid
operation inside the processor, such as illegal
opcode, address error (illegal memory
reference),arithmetic error (divide by zero,
overflow, etc).
3.Software Interrupts: are pseudo interrupts
providing a mechanism to implement the system
services which are accessed using the system calls.
The source of this is the program which accesses
the system service by executing a system call(ex:
INT instruction in 8086).

What is Software interrupts?

The Software interrupts are program
instructions. These instructions are inserted
at desired locations in a program. While
running a program, if software interrupt
instruction is encountered then the processor
executes an interrupt service routine.
What is Hardware interrupt?
If an interrupt is initiated in a processor by an
appropriate signal at the interrupt pin, then
the interrupt is called Hardware interrupt.

What is the difference between

Hardware and Software interrupt?
The Software interrupt is initiated by
the main program, but the Hardware
interrupt is initiated by an external
device.

Classification II
(Based On The Source Of
Interrupt)

1.Hardware Interrupts
2.Exception Interrupts
3.Software Interrupts
The interrupts can be again categorized as
maskable interrupts and non-maskable
interrupts.
Maskable interrupts can be enabled or disabled
using program instructions such as STI or CTI.
The signal on INTR line of 8086 is an example
of maskable interrupt.
The non-maskable interrupts can never be
disabled. Ex: NMI

Hardware Interrupts
Generated from an external signal applied to
NMI line or INTR input line of 8086.
The interrupt on INTR line can be disabled by
clearing the interrupt flag (IF) in the flag
register , i.e., if the IF is cleared CPU does not
respond to the signal on the INTR line.
CPU have an instruction to disable the
interrupts when a section of the code has to
run without being disturbed by external events.
Hence , most CPUs also have a special
interrupt called a Non- maskable interrupt
(NMI),which is serviced even when all the other
interrupts are disabled.
The NMI is used to signal emergencies such as
memory failure or power failure.

Exception Interrupt
A signal from some condition generated
in the 8086 by the execution of an
instruction.
Ex: Divide by zero interrupt
An attempt to perform division by zero
will automatically interrupt the
execution of the program.
Other examples: Divide overflow , An
illegal memory reference

Software Interrupts
Treated like hardware interrupts,
except that they are never disabled.
Use to implement the system call or
service instead of calling the
processor directly.
Example : Execution of Interrupt
instruction INT.

Interrupt Actions
The microprocessor checks to see if
any interrupt has been requested at
the end of each instruction cycle .
If the interrupt signal is sensed and
interrupt flag is set or the interrupt is
NMI , then 8086 performs ..

Interrupt Actions
Following are the actions initiated on the occurrence
of an interrupt:
1. Decrements the stack pointer by 2 and saves the flag register
onto the stack.[SP
SP 2; [SP]
flags ]
2. Clears the interrupt flag in the flag register to disable the INTR
interrupt. [IF
0]
3. Clears the trap flag in the flag register to stop generation of
the single step interrupt. [TF
0]
4. Decrement the stack pointer by 2 and saves the code segment
register onto the stack. [SP
SP 2; [SP]
CS]
5. Loads the code segment register with the segment address of
the interrupt service routine(ISR).[CS
segment of ISR ]
6. Decrement the stack pointer by 2 again and saves the
instruction pointer onto the stack. [SP
SP 2; [SP]
IP]
7. Loads instruction pointer with the offset address of the
interrupt service routine in the code segment of the ISR.[IP
offset of ISR]

Fig:8086 CPU Response To The

Interrupt
Mainline
Program

NMI /
INTR
/ INT
N

Push Flags
Clear IF,TF
Push CS
Push IP
Fetch ISR
Address;
CS = 0000:
[N*4]
IP = 0000:
[N*4+2]

Interrupt Service
Procedure
Push Registers

ISR Body

POP IP
POP CS
POP Flags
Pop Registers
IRET

How Does An Interrupt Work?

 The *86 family of processors can recognize

256 different interrupts.
It reserves the lowest 1024 bytes of
memory for a table containing the
addresses for each of the 256 possible
interrupts known as interrupt vector
(pointer)table.
Memory Addresses : 00000H to 003FFH
(IVT)

 Since 4 bytes are required to store

the CS and IP for each ISR , the table
can hold the starting addresses of
256 interrupt procedures.
The address of an ISR stored in
interrupt vector table is called as the
interrupt vector or interrupt pointer.

 The diagram shows the organization of 256

interrupt pointers in the memory table.
Each double word pointer (2 byte for IP
and 2 byte for CS) is identified by a
number from 0 to 255 known as type
number of the interrupt i.e. type N refers
to INT N whose ISR vector is stored at
memory location N * 4

 When an interrupt occurs (hardware, software or

exception), the processor multiplies interrupt
number by 4 and looks at the resulting memory
location to find the address of the piece of code
which handles the interrupt.
The processor saves the flag register and the current
address (CS,IP) in the program onto the stack,
disables IF, TF flags, and jumps to the beginning of
the interrupt handler.
When the interrupt handler completes its execution,
it invokes a special instruction (IRET) to handover
control to the interrupted process, by retrieving the
previously saved flags and return address from the
stack and places them back in the appropriate
registers in the CPU.

Fig: An Overview of
servicing of interrupt by
microprocessor

Current
program
execution

Interruptio
n

Push
flags,
return
address

Decode
the
interrupt

Duration
of ISR
execution

Execution
resumes
here

Points
to IVT

Interrupt
processing

Control
returns

Pop
return
addres
s and
flags

Execut
e ISR

Get
addres
s of ISR

 The interrupt handler has to be careful to

preserve the registers used by it.
The registers used to communicate the
result to the program that invoked the
interrupt need not be saved.
If the interrupt is triggered by a hardware
interrupt, then the interrupt handler has
to preserve all the registers, since registers
are not used to communicate the result to
the hardware interrupting system.

Interrupt Request Lines

(IRQ)

The microprocessor has to handle large no. of

tasks simultaneously and it would be
impossible for it to respond immediately to
every interrupt.
The Programmable Interrupt Controller (PIC)
known as CPU Receptionist is a special chip
that forms a queue and sends hardware
interrupts to the microprocessor one at a time.
Every hardware device which requests the
processors attention through an interrupt is
assigned with Interrupt Request Lines (IRQ).
It is a direct line to the PIC from hardware
device.

8086 Interrupt Types

1.Divide By Zero Interrupt (Type 0): When the
quotient from either a DIV or IDIV instruction is too
large to fit in the result register, 8086 will
automatically execute type 0 interrupt.
2.Single Step Interrupt (Type 1):in single step
mode, system will execute one instruction and
stop. We can check the contents of registers and
memory locations. If they are correct , we can tell
the system to go on and execute the next
instruction.
i.e. system will stop after it executes each
instruction and wait for further direction from user.

8086 Interrupt Types

3.Non Maskable Interrupt (Type 2):
The 8086 will automatically do a type 2 interrupt
response when it receives a low-to-high transition
on its NMI input pin.
When it does a type 2 interrupt ,8086 will push
the flags on the stack , reset TF and IF , and push
the CS value and IP value for the next instruction
on the stack.
It will then get the CS value for the start of the
type 2 interrupt-service procedure from address
0000AH and the IP value for the start of the
procedure from address 00008H.

8086 Interrupt Types

4.Breakpoint Interrupt (Type 3):
It is produced by execution of the INT 3
instruction.
The main use of type 3 interrupt is to
implement a breakpoint function in a system
Used in debugging
The system executes the instructions up to the
breakpoint and then goes to the breakpoint
procedure.
The breakpoint feature executes all the
instructions upto the inserted breakpoint and
then stops execution.

5.Overflow Interrupt (Type 4)

The type 4 interrupt is used to check
overflow condition after any signed
arithmetic operation in the system.
The 8086 overflow flag OF will be set if
the signed result of an arithmetic
operation on 2 signed no.s is too large
to be represented in the destination
register or memory location.

Interrupt Priorities
Interrupt

Priority

Divide Error, INT n,

INTO

Highest

NMI
INTR
Single Step

Lowest

 Microcomputer system design

requires that I.O devices such as
keyboards, displays, sensors and
other components receive servicing
in a an efficient manner so that large
amounts of the total system tasks
can be assumed by the
microcomputer with little or no effect
on throughput.

SKIP
The most common method of servicing such devices
is the Polled approach.
This is where the processor must test each device in
sequence and in effect ``ask'' each one if it needs
servicing.
It is easy to see that a large portion of the main
program is looping through this continuous polling
cycle and that such a method would have a serious
detrimental effect on system throughput, thus
limiting the tasks that could
be assumed by the microcomputer and reducing
the cost effectiveness of using such devices.

SKIP
A more desirable method would be one that would
allow the microprocessor to be executing its main
program and only stop to service peripheral
devices when it is told to do so by the device itself.
In effect, the method would provide an external
asynchronous input that would inform the
processor that it should complete whatever
instruction that is currently being executed and
fetch a new routine that will service the requesting
device.
Once this servicing is complete, however, the
processor would resume exactly where it left off.

SKIP
This method is called Interrupt .
It is easy to see that system
throughput would drastically
increase, and thus more tasks could
be assumed by the microcomputer to
further enhance its cost
effectiveness.

SKIP
The Programmable Interrupt Controller
(PIC) functions as an overall manager in an
Interrupt-Driven system environment.
It accepts requests from the peripheral
equipment, determines which of the
incoming requests is of the highest
importance (priority), determines whether
the incoming request has a higher priority
value than the level currently being
serviced, and issues an interrupt to the
CPU based on this determination.

SKIP
Each peripheral device or structure usually has a
special program or ``routine'' that is associated
with its specific functional or operational
requirements; this is referred to as a ``service
routine''.
The PIC, after issuing an Interrupt to the CPU,
must somehow input information into the CPU
that can ``point'' the Program Counter to the
service routine associated with the requesting
device. This ``pointer'' is an address in a
vectoring table and will often be referred
to, in this document, as vectoring data

SKIP

The 8259A is a device specifically designed for use in

real time, interrupt driven microcomputer systems.
It manages eight levels or requests and has built-in
features for expandability to other 8259A's (up to 64
levels).
It is programmed by the system's software as an I/O
peripheral.
A selection of priority modes is available to the
programmer so that the manner in which the requests
are processed by the 8259A can be configured to
match his system requirements.
The priority modes can be changed or reconfigured
dynamically at any time during the main program.
This means that the complete interrupt structure can
be defined as required, based on the total system
environment.

[End Intel Doc ]

Programmable Interrupt
Controller 8259A
Interrupts can be used for a variety of
applications.
Each of these interrupt applications requires a
separate interrupt input.
If we are working with 8086, we get only 2
inputs INTR and NMI.
For applications where we have multiple
interrupt sources, we use external device
called a priority interrupt controller [PIC] to
funnel the interrupt signals into a single
interrupt input on the processor.

Features Of 8259A
8 levels of interrupts.
Can be cascaded in master-slave configuration to handle
64 levels of interrupts.
Internal priority resolver.
Fixed priority mode and rotating priority mode.
Individually maskable interrupts.
Modes and masks can be changed dynamically.
Accepts IRQ, determines priority, checks whether incoming
priority > current level being serviced, issues interrupt
signal.
In 8085 mode, provides 3 byte CALL instruction. In 8086
mode, provides 8 bit vector number.
Polled and vectored mode.
Starting address of ISR or vector number is programmable.
No clock required.

Fig: Internal Block Diagram of

8259A

Architecture Of 8259A

1.Interrupt Request Register

[IRR]
The interrupts at IRQ input lines are
handled by Interrupt Request
Register internally.

IR stores all the interrupt requests in

it in order to serve them one by one
on the priority basis.

2.In-Service Register [ISR]

This stores all the interrupt requests
those are being served.

ISR keeps track of the requests being

served.

3.Priority Resolver
This unit determines the priorities of the
interrupt requests appearing simultaneously.
The highest priority is selected and stored
into the corresponding bit of ISR during INTA#
pulse.
The IR0 has the highest priority while the IR 7
has the lowest one, in fixed priority mode.
The priorities may be altered by
programming the 8259A in rotating priority
mode.

4.Interrupt Mask Register

[IMR]
This register stores the bits required
to mask the interrupt inputs.

IMR operates on IRR at the direction

of the Priority Resolver.

5.Interrupt Control Logic

This block manages the interrupt
and interrupt acknowledge signals to
be sent to the CPU for serving one of
the 8 interrupt requests.
This also accepts the interrupt
acknowledge (INTA) signal from CPU
that causes the 8259A to release
vector address on to the data bus.

6.Data Bus Buffer

This tristate bidirectional buffer
interfaces internal 8259A bus to the
microprocessor system data bus.
Control words, status and vector
information pass through data buffer
during read or write operations.

7.Read / Write Control Logic

This circuit accepts and decodes
commands from the CPU.

This block also allows the status of

the 8259A to be transferred on to the
data bus.

8.Cascade Buffer /
Comparator
This block stores
and compares the IDs of
all the 8259As used in the system.
3 I /O pins CAS 0-2 are outputs when the
8259A is used as a master.
The same pins act as inputs when the
8259A is in slave mode.
The 8259A in master mode sends the ID of
the interrupting slave device on these
pins.
The slave thus selected, will send its
preprogrammed vector address on the
data bus during the next INTA# pulse.

Pin Diagram Of 8259

Minimum Mode

Functional Description Of
8259 Signals

1. CS#: This is an active low chip select

signal for enabling RD# and WR#
operations of 8259A. INTA function is
independent of CS#.
2. WR# : This pin is an active-low write
enable input to 8259A. This enables it to
accept command words from CPU.
3. RD#: This is an active low read enable
input to 8259A. A low on this line
enables 8259A to release status onto
the data bus of CPU.

4. D7 D0 : These pins form a bidirectional

data bus that carries 8-bit data either to
control word or from status word registers.
This also carries interrupt vector
information.
5. CAS0 CAS2 Cascade Lines: A single
8259A provides 8 vectored interrupts. If
more interrupts are required , the 8259A is
used in cascade mode. In cascade mode, a
master 8259A along with 8 slaves 8259A
can provide up to 64 vectored interrupt
lines. These 3 lines act as select lines for
addressing the slaves 8259A.

6.SP# / EN#
Slave Program / Enable Buffer
Dual purpose pin
When the chip is used in buffered
mode, it can be used as an output to
control buffer transreceivers (EN).
If not in buffered mode it is used as
input to designate whether the chip is
used as:
a master (SP= 1) or a slave (EN = 0).

7.INT
This pin goes high whenever a valid
interrupt request is asserted.
This is used to interrupt the CPU and
is connected to the interrupt input of
CPU.

8.IR0 IR7
Interrupt Requests
These pins act as inputs to accept
interrupt requests to the CPU.
In edge triggered mode, an interrupt
service is requested by raising an IR
pin from a low to a high state and
holding it high until it is acknowledged,
just by latching it to high level, if used
in level triggered mode.

9.INTA#
Interrupt Acknowledge
This pin is an input used to strobe
in 8259A interrupt vector data on to
the data bus.
In conjunction with CS# , WR# , and
RD# pins , this selects the different
operations like, writing command
words, reading status words.

10. A0 ADDRESS LINE

This pin acts in conjunction with the
CS#, WR#, and RD# pins.
It is used by the 8259A to decipher
various Command Words the CPU
writes and status the CPU wishes to
read.
It is typically connected to the CPU
A0 address line (A1 for 8086, 8088).

8259A Pin Description

Interfacing Technique
Either Polling Or Interrupt Driven

Interrupt Sequence In 8086

The interrupt sequence in an 8086 8259A system is described
as follows:
1. One or more IR lines are raised high that set corresponding
IRR bits.
2. 8259A resolves priority and sends an INT signal to CPU.
3. The CPU acknowledges with INTA# pulse.
4. Upon receiving an INTA# signal from the CPU, the highest
priority ISR bit is set and the corresponding IRR bit is reset.
The 8259A does not drive data bus during this period.
5. The 8086 will initiate a second INTA# pulse. During this
period 8259A releases an 8-bit pointer on to data bus from
where it is read by the CPU.
6. This completes the interrupt cycle. The ISR bit is reset at the
end of the second INTA# pulse if automatic end of interrupt
(AEOI) mode is programmed. Otherwise ISR bit remains set
until an appropriate EOI command is issued at the end of
interrupt subroutine.

Fig:8259A Connected To An 8086

8086

8259A

AD0

D0

IR0

D7
INTA#

IR7
INT

AD0

AD7
INTR
INTA#

Interrupt
Input

8259A Overview & System

Connections
If 8086 interrupt flag is set and the INTR input receives a
high signal , the 8086 will
1. Send out two interrupt acknowledge pulses on its INTA#
pin to the INTA# pin of 8259A PIC. The INTA# pulses tell
the 8259A to send the desired interrupt type to the
8086 on the data bus.
2. Multiply the interrupt type it receives from the 8259A
by 4 to produce an address in the interrupt vector
table.
3. Push the flags on the stack.
4. Clear IF and TF.
5. Push the return address on the stack.
6. Get the starting address for the interrupt procedure
from the interrupt-vector table and load that address in
CS and IP.
7. Execute the interrupt service procedure.

 8-bit data bus allows the 8086 to send

control word to the 8259A and read a
status word from the 8259A.The RD#
and WR# inputs control these transfers
when the device is selected by asserting
its chip select (CS#) input low.
The 8-bit data bus also allows the 8259A
to send interrupt types to the 8086.

 Eight interrupt inputs labeled IR0 through

IR7 .
If 8259A is properly enabled, an interrupt
signal applied to any one of these inputs
will cause the 8259A to assert its INT
output pin high.
If this pin is connected to the INTR pin of an
8086 and if the 8086 interrupt flag is set ,
then the high signal will cause the INTR
response.

PROGRAMMING THE 8259A

The 8259A accepts two types of
command words generated by the CPU:
1. Initialization Command Words (ICWs)
2. Operation Command Words (OCWs)

1. Initialization Command Words (ICWs): Before

normal operation can begin, each 8259A in the
system must be brought to a starting point -by a
sequence of 2 to 4 bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are
the command words which command the 8259A to
operate in various interrupt modes. These modes
are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode

The OCWs can be written into the 8259A anytime

after initialization.

Command Words Of 8259A

The command words of 8259A are
classified in 2 groups:
1.Initialization command words [ICWs]
2.Operation command words [OCWs]

Initialization command words

[ICWs]
Before it starts functioning, the 8259A must
be initialized by writing two to four command
words into the respective command
registers.
These are called as initialization command
words [ICWs].
If A0= 0 and D4 = 1, the control word is
recognized as ICW1.
ICW1 contains the control bits for edge / level
triggered mode, single / cascade mode, call
address interval and whether ICW 4 is
required or not, etc.

 If A0 = 1, the control word is

recognized as ICW2.
The ICW2 stores details regarding
interrupt vector addresses.
The initialization sequence of 8259A
is described in the form of flow chart
in next slide.

Fig: Initialization Sequence Of

8259A

 Master/Slave in ICW4 is only used in

the buffered mode.

Level Triggered Mode Vs. Edge

Triggered Mode
In level triggered mode, service will
be requested whenever a high level
is present on an IR input.
In edge-triggered mode, a signal on
an IR input must go from low to high
and stay high until serviced.

Fig: Initialization Command Word ICW1

ICW1
A0

D7

A7

D6

D5

D4

D3

D2

A6

A5

LTI
M

ADI

D1

D0

SN
GL

IC4

A7 A5 of interrupt
vector address
MCs 80/85 modes
only

1 = ICW4 needed
0 = No ICW4 needed

1 Single
0 Cascaded

1 Level Triggered
0 Edge Triggered

Dont Care

Call Address Interval

1 Interval of 4 bytes
0 Interval of 8 bytes

Initialization Sequence

Once ICW1 is loaded , the following

initialization procedure is carried out
internally:
a)The edge sense circuit is reset, i.e. by default
8259A interrupts are edge sensitive.
b)IMR is cleared.
c)IR7 input is assigned the lowest priority.
d)Slave mode address is set to 7.
e)Special mask mode is cleared and status read
is set to IRR.
f) f) If IC4 = 0 , all the functions of ICW4 are set to
zero. Master / slave bit in ICW4 is used in the
buffered mode only.

ICW2
In 8086 based system A15 - A11 of the
interrupt vector address are inserted
in place of T7 - T3 respectively.
The remaining 3 bits (A8,A9, A10) are
selected depending upon the
interrupt level, i.e. from 000 to 111
for IR0 to IR7.

Fig: Initialization Command Word ICW2

ICW2
A0

D7

D6

D5

D4

D3

D2

D1

D0

T7

T6 T5 T4 T3 A1 A9 A8
0

In 8086/88 based system A15 A11 of the interrupt vector

address inserted in place of T7 T3 respectively and the
remaining 3 bits A8 A10
A10 A9, A8 Selected according to interrupt request level.
They are not the address lines of Microprocessor
A0 =1 selects ICW2

Note
Compulsory command words in

initialization sequence of 8259A :

ICW1 and ICW2
Optional command words :
ICW3 and ICW4

ICW3
ICW3 is read only when there are more
than one 8259As is in the system , i .e .
cascading is used (SNGL = 0).
The SNGL bit in ICW1 indicates whether
the 8259A is in cascade mode or not.
The ICW3 loads an 8-bit slave register.

ICW3 In Master Mode

In master mode [i.e. SP# = 1 or in
buffer mode M / S = 1 in ICW4], the
8-bit slave register will be set bit-wise
to 1 for each slave in the system.
The requesting slave will then release
the second byte of a CALL sequence
released by it on the Data Bus .

Master mode ICW3

A0

D7

D6

D5

D4

D3

D2

D1

D0

1 S7 S6 S5 S4 S3 S2 S1 S0
Sn = 1 -- IRn Input has a slave
= 0 IRn Input does not have a
slave

Slave mode ICW3

A0

D7

D6

D5

D4

D3

D2D1D0 000 to 111 for IR0 to IR7

D2

D1

D0

ID ID ID
2 1 0
or slave 1 to slave 8

Fig: ICW in Master & Slave Mode

ICW3 In Slave Mode

In slave mode [ SP# = 0 or if BUF = 1
and M/S = 0 in ICW4] bits D2 to D0
identify the slave, i.e. 000 to 111 for
slave 1 to slave 8.
The slave compares the cascade inputs
with these bits and if they are equal,
the second byte of the CALL sequence
is released by it on the data bus.

ICW4
The use of this command word
depends on the IC4 bit of ICW1.
If IC4=1, ICW4 is used, otherwise it is
neglected.

ICW4
A0
1

D7
0

D6
0

D5
0

D4
SFN
M

1
=

Auto EOI Mode

0
Normal EOI
=D2ModeD1

D3
D0
BUF M/S AEO P
I
M

1
=

Special Fully Nested Mode

1
=

8086 / 8088
Mode

0
=

Not Special Fully Nested

Mode

0
=

MCS 80 / 85
Mode

0 X Non Buffered Mode

1 0 Buffered Mode /
Slave
1 1 Buffered Mode /
Master

Fig: ICW4 Bit Functions

ICW4
The bit functions of ICW4 :
1.SFNM:
Special fully nested mode is selected.
If BUF = 1, the buffered mode is selected.
In the buffered mode, SP/EN acts as enable
output and the master/slave is determined
using the M/S bit of ICW4.

2. M/S:

If M/S = 1, 8259A is a master.

If M/S =0, 8259A is slave.
If BUF = 0, M/S is to be neglected.

ICW4
3. AEOI:
If AEOI = 1, the automatic end of
interrupt mode is selected.

4.PM :
If the PM bit is 0, the MCS-85 system
operation is selected.
If PM=1, 8086/88 operation is
selected.

Operation Command
Words
Once 8259A is initialized using the command
words for initialization , it is ready for its normal
function
The chip 8259A is ready to accept interrupt
requests at its input lines.
8259A has its own way of handling the received
interrupts called as modes of operation.
These modes of operations can be selected by
programming.
Writing 3 internal registers called as
operation command word registers.

OCWs
The data written into the operation
command word registers (bit pattern) is
called as operational command words.

In the three operation command words

OCW1, OCW2 and OCW3, every bit
corresponds to some operational
feature of the mode selected, except
for a few bits those are either 1 or 0.

Fig: Operation Command

Words

OCW1
A0
1

D7
M7

D6
M6

D5
M5

D4
M4

D3
M3

D2
M2

D1
M1

D0
M0

1 Mask Set
0 Mask Reset

Use: To mask the unwanted interrupt requests.

If the mask bit is :
0, the corresponding interrupt request is
enabled
1, the request is disabled.

 OCW1 sets and clears the mask

bits in the Interrupt Mask
Register (IMR).

OCW2
In OCW

the 3 bits, R, SL and EOI control

the end of interrupt, the rotate mode and
their combinations.
2

The three bits L2, L1 and L0 in OCW2

determine the interrupt level to be selected

for operation, if SL bit is active i.e. 1.
Used to reset a bit in the in-service register.

OCW2
A0 D7 D6 D5

D4

D3

1 R

S E
L OI

D2
L2

D1
L1

D0
L0
IR NO.

Non-Specific EOI COMMAND

SPECIFIC EOI COMMAND

ROTATE ON NONSPECIFIC EOI

COMMAND

ROTATE IN AUTOMATIC EOI MODE

[SET]

ROTATE IN AUTOMATIC EOI [CLEAR]

ROTATE ON SPECIFIC EOI COMMAND

SET PRIORITY COMMAND*

NO OPERATION

0 12 3 4 5 6 7
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1

* - In this Mode L0 L2 are used

OCW3
In operation command word 3 (OCW 3), if
the ESMM bit, i.e. enable special mask
mode bit is set to 1, the SMM bit is enabled
to select or mask the special mask mode.
When ESMM bit is 0 the SMM bit is
neglected.
If the SMM bit, i.e. special mask mode bit
is 1, the 8259A will enter special mask
mode provided ESMM=1.

OCW3
ESMM : Enable Special Mask Mode.
When ESMM =1 it enables the SMM
bit to set or reset the Special Mask
Mode.
When ESMM = 0 the SMM bit becomes
a don't care .

OCW3
SMM: Special Mask Mode
If ESMM = 1 and SMM = 1 the 8259A
will enter Special Mask Mode.
If ESMM = 1 and SMM = 0 the 8259A
will revert to normal mask mode.
When ESMM = 0, SMM has no effect.

OCW3
A0

D7

D6

D5

ESM SMM
M
0

Reset Special
Mask

Set Special
Mask

No Action

D4

1 Poll
Command
0 No Poll
Command

D3

D2

D1

D0

RR

RIS

No

Action

Read IRR on
next RD# pulse

Read ISR on
next RD# pulse

OCW3
If ESMM=1 and SMM=0, the 8259A
will return to the normal mask mode.

Operating Modes of 8259

The different modes of operation of
8259A can be programmed by
setting or resting the appropriate bits
of the ICW or OCW.

The different modes of

operation of 8259A
1.Fully Nested Mode
2.End of
Interrupt (EOI)
3. Automatic
Rotation
4.Automatic EOI
Mode
5.Specific
Rotation
6.Specific Mask Mode

7.Edge & Level Triggered

Mode
8.Reading 8259 Status
9.Poll Command
10.Special Fully Nested
Mode
11.Buffered Mode
12.Cascade Mode

1.Fully Nested Mode

Default mode of operation of 8259A
This mode is entered after initialization unless
another mode is programmed.
IR0 has the highest priority and IR7 has the
lowest.
When interrupt requests are noticed, the highest
priority request amongst them is determined
and the vector is placed on the data bus.
The corresponding bit of ISR is set and remains
set till the microprocessor issues an EOI
command just before returning from the service
routine or the AEOI bit is set.

1.Fully Nested Mode

If the ISR (in service) bit is set, all the
same or lower priority interrupts are
inhibited but higher levels will generate
an interrupt, that will be acknowledge
only if the microprocessor interrupt
enable flag IF is set.
The priorities can afterwards be
changed by programming the rotating
priority modes.

2.End of Interrupt (EOI)

The ISR bit can be reset either with AEOI bit
of ICW4 or by EOI command, issued before
returning from the interrupt service routine.
There are two types of EOI commands
specific and non-specific.
When 8259A is operated in the modes that
preserve fully nested structure, it can
determine which ISR bit is to be reset on EOI.
When non-specific EOI command is issued to
8259A it will be automatically reset the
highest ISR bit out of those already set.

2.End of Interrupt (EOI)

When a mode that may disturb the fully
nested structure is used, the 8259A is no
longer able to determine the last level
acknowledged.
In this case a specific EOI command is
issued to reset a particular ISR bit.
An ISR bit that is masked by the
corresponding IMR bit, will not be cleared
by non-specific EOI of 8259A, if it is in
special mask mode.

3.Automatic Rotation
This is used in the applications where all
the interrupting devices are of equal
priority.
In this mode, an interrupt request IR level
receives lowest priority after it is served
while the next device to be served gets
the highest priority in sequence.
Once all the device are served like this,
the first device again receives highest
priority.

4.Automatic EOI Mode

Till AEOI=1 in ICW4, the 8259A
operates in AEOI mode.
In this mode, the 8259A performs a
non-specific EOI operation at the
trailing edge of the last INTA pulse
automatically.
This mode should be used only when a
nested multilevel interrupt structure is
not required with a single 8259A.

5.Specific Rotation
In this mode a bottom priority level
can be selected, using L2, L1 and L0
in OCW2 and R=1, SL=1, EOI=0.
The selected bottom priority fixes
other priorities.

5.Specific Rotation
If IR5 is selected as a bottom priority,
then IR5 will have least priority and
IR4 will have a next higher priority.
Thus IR6 will have the highest priority.
These priorities can be changed
during an EOI command by
programming the rotate on specific
EOI command in OCW2.

6.Specific Mask Mode

In specific mask mode, when a mask
bit is set in OCW1, it inhibits further
interrupts at that level and enables
interrupt from other levels, which are
not masked.

7.Edge and Level

Triggered Mode
This mode decides whether the
interrupt should be edge triggered or
level triggered.
If bit LTIM of ICW1 =0 they are edge
triggered, otherwise the interrupts
are level triggered.

8.Reading 8259 Status

The status of the internal registers of
8259A can be read using this mode.
The OCW3 is used to read IRR and ISR
while OCW1 is used to read IMR.
Reading is possible only in no polled
mode.

9.Poll Command
In polled mode of operation, the INT output of
8259A is neglected, though it functions
normally, by not connecting INT output or by
masking INT input of the microprocessor.
The poll mode is entered by setting P=1 in
OCW3.
The 8259A is polled by using software
execution by microprocessor instead of the
requests on INT input.
The 8259A treats the next RD# pulse to the
D7
D6
D5
D4
D3
D2
D1
D0
8259A
as
interrupt
I
X an X
X
Xacknowledge.
W2
W1
W0
If = 1, there is an
interrupt

Binary code
of highest
priority level

Fig: data Word Of 8259

9.Poll Command
An appropriate ISR bit is set, if there is a
request.
The priority level is read and a data word is
placed on to data bus, after RD# is
activated.
A poll command may give more than 64
priority levels.
[This has nothing to do with the 8086
interrupt structure and the interrupt
priorities.]

10.Special Fully Nested

Mode

This mode is used in more complicated system,

where cascading is used and the priority has to
be programmed in the master using ICW 4.
This is somewhat similar to the normal nested
mode.
In this mode, when an interrupt request from a
certain slave is in service, this slave can
further send request to the master, if the
requesting device connected to the slave has
higher priority than the one being currently
served.

10.Special Fully Nested

Mode
In this mode, the master interrupt the
CPU only when the interrupting device
has a higher or the same priority than the
one current being served.
In normal mode, other requests than the
one being served are masked out.
When entering the interrupt service
routine the software has to check whether
this is the only request from the slave.

10.Special Fully Nested

Mode
This is done by sending a non-specific
EOI can be sent to the master,
otherwise no EOI should be sent.
This mode is important, since in the
absence of this mode, the slave
would interrupt the master only once
and hence the priorities of the slave
inputs would have been disturbed.

11.Buffered Mode
When the 83259A is used in the
systems where bus driving buffers
are used on data buses.
The problem of enabling the buffers
exists. The 8259A sends buffer
enable signal on SP/ EN pin,
whenever data is placed on the bus.

12.Cascade Mode
The 8259A can be connected in a system
containing one master and eight slaves
(maximum) to handle up to 64 priority levels.
The master controls the slaves using CAS0CAS2 which act as chip select inputs
(encoded) for slaves.
In this mode, the slave INT outputs are
connected with master IR inputs.
When a slave request line is activated and
acknowledged, the master will enable the
slave to release the vector address during
second pulse of INTA sequence.

12.Cascade Mode
The cascade lines are normally low and contain
slave address codes from the trailing edge of
the first INTA pulse to the trailing edge of the
second INTA pulse.
Each 8259A in the system must be separately
initialized and programmed to work in different
modes.
The EOI command must be issued twice, one for
master and the other for the slave.
A separate address decoder is used to activate
the chip select line of each 8259A.

 Following Fig shows the details of the circuit

connections of 8259A in cascade scheme.

INTERRUPT SEQUENCE
OUTPUTS
MCS-80, MCS-85
This sequence is timed by three INTA
pulses.
During the first INTA# pulse the CALL
opcode is enabled onto the data bus.

 During the second INTA pulse the lower

address of the appropriate service routine
is enabled onto the data bus.
When Interval = 4, bits A5-A7 are
programmed, while A0- A4 are
automatically inserted by the 8259A.
When Interval = 8 only A6 and A7 are
programmed, while A0-A5 are
automatically inserted

8086, 8088
8086 mode is similar to MCS-80 mode
except that only two Interrupt Acknowledge
cycles are issued by the processor and no
CALL opcode is sent to the processor.
The first interrupt acknowledge cycle is
similar to that of MCS-80, 85 systems in
that the 8259A uses it to internally freeze
the state of the interrupts for priority
resolution and as a master it issues the
interrupt code on the cascade lines at the
end of the INTA pulse.

 On this first cycle it does not issue any

data to the processor and leaves its data
bus buffers disabled.
On the second interrupt acknowledge
cycle in 8086 mode the master (or slave if
so programmed) will send a byte of data
to the processor with the acknowledged
interrupt code composed as follows
(note the state of the ADI mode control is
ignored and A5 - A11 are unused in 8086
mode

Interfacing & Programming

8259
Problem: Show 8259A interfacing connections
with 8086 at the address 074x. Write an ALP
to initialize the 8259A in single level
triggered mode, with call address interval of
4, non-buffered, no special fully nested
mode. Then set the 8259A to operate with
IR6 masked,IR4 as bottom priority level, with
special EOI modes. Set special mask mode
of 8259A. Read IRR and ISR into registers BH
and BL respectively.

 Solution: Let the starting vector address is

0000:0010. The interconnections of 8259A
with 8086 are shown in fig below:
A0

D7

D6

D5

D4

D3

D2

D1

D0

Always
set to 0

dont care for

8086 system

always
set to 1

ICW1 = 1F

ICW4 needed
Single 8259A

The 8086 is interfaced with lower

byte of the 8086 data bus, hence A0
line of the microprocessor is
abandoned and A1 of the
microprocessor is connected with
A0 of the 8259A

Call address
interval of 4
Level
triggered
mode

ICW2

vector address = 0000:0010 for IR3

T7

T6

T5

T4

T3

A10

A9

A8

= 83 H
IR3 Selected

There is no slave hence the ICW3 is as given below:

A0

D7

D6

D5

D4

D3

D2

D1

D0

ICW3= 0 0H

Actually ICW3 is not at all needed, because in ICW1 the 8259A is set for single
mode.
The ICW4 should be set as shown below:

A0

D7

D6

D5

D4

D3

D2

D1

D0

For special fully nested

mode masking
Non buffered
mode

ICW4= 0 1H
For 8086 system
Normal EOI

The OCW1 sets the mask of IR6 as below:

A0

D7

D6

D5

D4

D3

D2

D1

D0

OCW1 = 40H

IR6 masked
The OCW2 sets the modes and rotating priority as shown below:
A0 D7 D6 D5 D4 D3 D2 D1 D0 OCW2 = E4H
0

0
Bottom Priority
Level set at IR4

Specific EOI Command

with rotating priority

The OCW3 sets the special mask mode and reads ISR and IRR using the following
control words.
For reading IRR:
A0

D7

D6

D5

D4

D3

D2

D1

D0

Special
mask mode

Read IRR

No Poll
OCW3 = 6AH

A0

D7

D6

D5

D4

D3

D2

D1

D0

OCW3 = 6BH

Read
ISR

Disk Operating System

Refer Advanced MSDOS
Programming By Ray Dunkan,
page No. 4 to page No. 45

DOS

An OS that provides general, device-independent

access to the resources of a computer.
Devices: keyboards, screens, disk drivers
Device independent: no need to address devices
specifically, since DOS & its device drivers can
handle the operation at the device level.
DOS Functions:
1.File Management
2.Input / Output
3.Program Loading
4.Memory Management
5.Interrupt Handling

The Structure Of MS-DOS

MS DOS is partitioned into several
layers that serve to isolate the kernel
logic of OS, and the users perception of
the system, from hardware it is running
on.
These layers are:
1.The BIOS (Basic Input / Output System)
2.The DOS kernel
3.The command processor (Shell)

The BIOS Module

Specific to individual computer system
Is provided by the manufacturer of the
system.
It contains default resident hardware
dependent drivers for the following devices:
1.Console display and keyboard (CON)
2.Line printer (PRN)
3.Auxiliary device (AUX)
4.Date and time (CLOCK$)
5.Boot disk device (Block device)

BIOS Module
MS-DOS kernel communicates with these
device drivers through I/O request packets
Then translate the drivers these requests into
proper commands for the various hardware
controllers.
Most primitive parts of hardware drivers are
located in ROM so that they can be used by
stand-alone applications ,diagnostics , and the
system startup programs.
Resident drivers : drivers built into BIOS
Installable drivers: installed during system
initialization by DEVICE command in

Organization Of DOS
4 major components
1. IO.SYS:
a.
b.
c.

Performs initialization functions at boot up time

Contains device drivers that supplement the primitive I/O
support in ROM BIOS.
Store on a disk as a hidden system file

2. MSDOS.SYS:
a.
b.

Acts as DOS kernel

Concern with file management, memory management, and
input/output.

3. COMMAND.COM:
a.
b.
c.

A command processor or shell

Interface between user and OS
Displays DOS prompt, monitors the keyboard and processes
user commands

4. Boot Sector

Map Of Conventional
Memory
640K

COMMAND.COM transient portion

(executing programs may erase it)
Available for programs use
COMMAND.COM resident portion (resides permanently )
System files IO.SYS and MSDOS.SYS
BIOS data area

0K

Interrupt service table

DOS BIOS Interface

BIOS contains a set of routines in ROM to
provide device support.
BIOS tests and initializes attached
devices and provides services that are
used for reading to and for writing from
the devices.

DOS BIOS Interface

User Programs
DOS
BIOS
Hardware / Devices

System Program Loader

DOS supports 2 types of executable
programs:
1) .COM
2) .EXE
A .COM program consists of one segment
that contains code, data and the stack. Max
size 64K
An .EXE program may be virtually any size
and it consists of separate code, data and
stack segments and 512-byte header
present

 A .COM program is an absolute

image of the executable program,
but with relocatable address
information.

Segments
Stack: Need to define an .EXE program with a
stack segment, whereas a .COM program
automatically generates a stack.
Data : An .EXE program usually defines a data
segment and initializes the DS register with the
address of that segment. Since the data for a
.COM program is defined within the code
segment, no need to define the data segment
either.
Code :An either .COM program combines the
PSP, stack , data segment, and code segment
into one code segment , in a maximum of 64K
bytes.

Initialization
When DOS loads a .COM program for execution ,
it automatically initializes all segment registers
with the address of PSP. Since the CS and DS
registers will contain the correct initial segment
address, the user program does not have to load
them.
Because addressing begins at an offset of 100H
bytes from the beginning of the PSP, code an
ORG directive as ORG 100H immediately
following the code SEGMENT or .CODE statement.
The ORG directive tells the assembler to begin
generating the object code at an offset of 100H
bytes past the start of the PSP, where the
actual .COM program begins.

What Is Program Segment Prefix

DOS loads .COM and .EXE programs for
execution into a program segment and
creates a PSP at offset 00H and the program
itself at offset 100H of the segment.

00 01 H

An INT 20H instruction (CD20H) to facilitate the return to DOS

02 03H

The segment address of the last paragraph of memory allocated

to the program, as xxxx0. For ex: 640K is indicated as 00A0H,
meaning A0000[0]

04 09H

Reserved by DOS

0A 0DH

Terminate address (segment address for INT 22H)

0E 11H

Ctrl + Break exit address (segment address for INT 23H)

12 15H

Critical error exit address (segment address for INT 24H)

16 17H

Reserved by DOS

18 2BH

Default File Handle Table

2C 2DH

Segment address of programs environment

2E 31H

Reserved by DOS

32 33H

Length of the File Handle Table

34 37H

Far Pointer to the handle table

38 4FH

Reserved by DOS

50 51H

Call to DOS function (INT 21H and RETF)

52 5BH

Reserved by DOS

5C 6BH

Parameter area 1, formatted as a standard unopened FCB (#1)

6C 7FH

Parameter area 2, formatted as a standard unopened FCB (#2);

overlaid if the FCB at 5CH is opened

80 FFH

Buffer for a default DTA (Command line string)

SS:SP

Stack grows downward from top

of segment

Program code and data

CS:0100H

CS: 0000H
DS:0000H
ES:0000H
SS:0000H

Program segment prefix

Fig: A Memory Image of a

typical .COM type program
after loading

SS:SP

SS:0000H

CS:0100H

DS:0000H
ES:0000H

Stack segment ; stack grows

downward from top of segment

Data segment
Program code
Program segment prefix

Fig: A Memory Image of a

typical .EXE type program
immediately after loading

File Handles
A file handle is simply a number that refers to
a specific device.
DOS delivers a file handle when you open a
file for input or create a file for output.
The operation involves the use of an ASCIIZ
string and DOS function 3CH or 3DH.
The file handle is a unique one-word number
returned in the AX that we save in a word data
item and use for all subsequent requests to
access file.

PSP 18 2BH : Default File Handle

Table

Each byte in the 20-byte default file handle table

refers to an entry in a DOS table that defines the
related device or driver.
Initially, the table contains 0101010002FFFF,
where the first 01 refers to the keyboard, the
second 01 to the screen, and so on.
The table of 20 handles so DOS allows a
maximum of 20 files open at one time.
TABLE DEVICE

HANDLE DEVICE

01

Console

Keyboard (Standard
input)

01

Console

Keyboard (standard
output)

01

Console

Screen (standard error)

00

COM1(Serial
port)

Auxiliary

PSP 80 FFH : Default DTA Buffer

This portion of PSP is called a default buffer for
the DTA

ASCIIZ Strings
Tell DOS the address of an ASCIIZ string containing the
location of the file: disk drive, directory path, and
filename
All are optional and within apostrophes
Followed by a byte of hex zeros
So the name given
The max length of the string is 128bytes
The following code defines a drive and filename:
PATHNAM1 DB D:\Test.asm,00H

The backslash acts as a path separator.

A byte of zeros terminates the string.
For interrupts that require an ASCIIZ string, load its offset address
in the DX register
LEA DX,PATHNAME

Interrupts
1. To Get the address of PSP:
mov ah,51h

;Request address of PSP

int 21h
;Call DOS
mov ES,BX ; Save PSP address in ES
By determining the address of PSP, the data can
be accessed in order to process specified files or
to take special action.
DOS function 51H delivers to the BX register the
segment address of current PSP.
The above code gets address of PSP and stores
it in ES register.

2) Create File :- INT 21H, 3CH

MOV AH, 3CH

; Request create file
LEA DX, filename
MOV CX, file attribute

INT 21H

; ASCIIZ string
; (0000-> NORMAL, 0001->READ
ONLY, 0002-> HIDDEN )
; Call DOS

Given a proper pathname it creates a new file in

designated directory.
If the specified file already exits, it is truncated to
zero length.
In either case, the file is opened and a handle is
returned that can be used by the program for
subsequent access to the file.

3) Open File: INT21H, 3DH

MOV AH, 3DH

; Request open file
MOV AL, ACCESS MODE; (00-> Read, 01->Write,10>Read/write)
LEA DX, fname
; Address of pathname
INT 21H
; Call DOS

If a file with the given filename exists, the operation sets

the record length to 1,assumes the files current
attribute, sets the file pointer to 0,clears the carry flag,
and sets a handle for the file in the AX which is to be
used for all subsequent operations.
If the file does not exist, the operation sets the carry flag
and returns an error code in the AX.

4) Read File: INT 21H, 3FH

MOV AH, 3FH

MOV BX, Handle
MOV CX, Length
LEA DX, IPREC
INT 21H

; Request read record

; File handle
; Record length
; Address of input record
; Call DOS

This function is used to read the contents of

the file. The number of bytes to be read ,
and the address of the input area is passed
into the register CX and DX respectively.
A valid operation delivers the record to the
program, clears the carry flag, and sets the
AX to the number of bytes actually read.

DOS commands
Internal / External Commands

 The user commands that are

accepted by COMMAND.COM fall into
3 categories:
1.Internal commands
2.External commands
3.Batch commands

Internal Command
Internal Commands
External Commands

INTERNAL DOS COMMANDS

Internal Commands are located in memory
and do not require further disk access when
they are used.
COPY, DEL, DIR, VER, TYPE, PRINT,REN
Intrinsic commands those are carried out
by code embedded in COMMAND.COM itself.
the routines for the internal commands are
included in transient part of
COMMAND.COM

EXTERNAL DOS COMMANDS

They reside on the DOS disk and require a disk
access to be used
CHKDSK, FORMAT, DISKCOPY ,MD,CD,RD
Extrinsic commands or transient programs are
the names of the programs stored in disk files.
Before their execution, these programs must be
loaded from the disk into the transient program
area (TPA) of memory.
As soon as an external command has completed
its work, it is discarded from memory; hence it
must be reloaded from disk each time it is
invoked.

FORMAT
NEW DISKS MAY BE FORMATTED
ALREADY OR NOT
USING THE FORMAT COMMAND
INITIALIZES; BY WRITING CODE ON IT
TO ASSIGN TRACKS AND SECTORS
WHERE YOUR DATA WILL BE STORED.
FORMAT ERASES AND CHECKS OLD
DISKS FOR ERRORS

DIRECTORY
THE DIR COMMAND IS AN INTERNAL
DOS COMMAND USED TO LIST
CONTENT
DIR
DIR/W
DIR/P

COPY COMMAND
THE COPY COMMAND MAKES A
SECOND COPY OF A FILE ONTO
ANOTHER DESTINATION
IF YOU WANT TO COPY SOMETHING
FROM ONE DIRECTORY TO A DISK
YOU MUST BE IN THAT DIRECTORY
COPY DOES NOT ERASE THE
ORIGINAL

DEL OR ERASE
REMOVES DATA
WINDOWS 95 IS HELPFUL FOR THIS
ONCE ERASED , A FILE CANNOT BE
RECOVERD UNLESS USE A SPECIAL
UTILITY LIKE NORTON UTILITIES

TYPE
LIST OR TYPES THE CONTENTS OF A
FILE ON THE SCREEN
USEFUL FOR ; BAT, TXT,

MKDIR(MD), CHDIR(CD) ,
RMDIR(RD)

MD MAKES A DIRECTORY
CD CHANGES DIRECTORY
RD REMOVES A DIRECTORY
EXAMPLES

Batch Files
Text files that contain lists of other
intrinsic , extrinsic , or batch
commands.
These files are processed by a special
interpreter that is built into the
transient portion of COMMAND.COM.
The interpreter reads the batch file
one line at a time and carries out each
of the specified operations in order.

TSR Programs
It is a DOS program that on execution is
loaded in the memory and is resident in the
memory till it is removed or system is reboot.
Present in the memory even if not active
Other programs (transient) run and free the
memory block in use after completion or
system aborting them.
TSR performs the task in background
Many TSRs in memory at a time
Typically include clocks, calculators, screen
savers

TSR
While running another program in DOS , press the
present keyboard key or the combination of keys
and TSR program will pop up in view.
Can be loaded any time
Mostly no option for unloading so stay in memory
Active TSR: responds to a h/w interrupt e.g. pop up
programs
Passive TSR: activated in response to an explicit
call from an executing application program. They
contain a callable library of routines. They can also
extend some BIOS or DOS call. E.g. mouse driver.

Q1 Services provided by DOS :

i.File Management
ii.Memory Management
iii.Program Loading
iv.Input / Output
a.None of above
c. I & ii only

b.All of above
d.iii & iv

Q2. Which is an absolute image of the

executable program?
a. A .COM b. A .EXE c. PSP d. All
a,b,c

Q3. The difference (s) between .COM

file and .EXE file is /are:
1.Size of file
2.No. of Segments present in each file
3.512 byte header
4.PSP before file start
a . All of above
b. None of above
c. 1,2,3 Only d. 3 only

Q4. Types of TSR program is / are:

a. 1 b. 2 c. 3

d.4

Q5. Which cache is used to speed up

the paging operation in the computer
memory?
a. TBL b.TLB
All of these

c.Page table

d.

Q6. The registers pushed onto the

stack due to ISR execution are:
a.CS
b. CS,IP
c. CS, IP, FLAGS
d. CS, IP, TF,IF

Q7. Which flag is responsible for single

step execution of program?

a.IF
b.Trap Flag
c.Direction Flag
d.All of above

Q8. 8259A chip is a:

a.Timer
b.Microcontroller
c.Microprocessor
d. Programmable Interrupt Controller

Q9. With reference to 8259A IRR, PR, ISR, IMR

stands for:
a.Interrupt Request Register, Priority Resolver, In
Service Register, Interrupt Mask Register respectively.

b. Interrupt Request Register, Priority Register, In

Service Register, Interrupt Mask Register respectively.
c. Interrupt Request Register, Priority Resolver, In
Service Register, Input Mask Register respectively.
d. Interrupt Request Register, Priority Resolver,
Interrupt Service Register, Interrupt Mask Register
respectively.

Q.10 For masking the interrupt

requests the operational command
word used is:
a. OCW1
b. OCW2
None of above

3.OCW3

4.

Answer Key
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10

b
a
c
b
B
c
b
d
a
a

i7
Q1. Which of the following statement(s) is /
are true about the 64-bit RFLAGS register in
i7 ?
i.Lower 32-bits same as EFLAGS register
ii.Upper 32 bits are reserved
iii.Lower 32 bits are reserved
a.All of above
b.None of above
c.i only
d.i & ii

i7
Q2. Which of the following statement(s) is/
are true related to features of i7?
i.Nehalem microarchitecture support with QPI
ii.64 bit RIP
iii.On chip FPU
iv.8MB L3 cache shared by all 4 cores
a. None of above
b. i & ii
c. i ,ii, iv
d. all of
above

Instruction Set
Q3 the versions of REP instructions:
i.REPE , REPZ
ii.REPNE, REPNZ

a. i only
None

b. ii only

c. i & ii

d.

Instruction Set
Q4 Macro and Procedure
i.Like macro procedure expands at the
place of call in the program
ii.Like procedure macro need stack
operation to store return address
a.Both are true
c. Only i is true

b. both are false

d. only ii is true