ADIABATIC TECHNIQUE

FOR
LOW POWER VLSI

Submitted by:
Submitted to:
Anamika Pancholi
02702072014
Ashwani kumar
Dept.
M.Tech(VLSI Design)
GDTUW, Delhi
20142016

HODDrECE

Why low power?

Desirability of portable devices.
Advent of hand held battery operated
devices.
Large power dissipation requires larger
heat sinks hence increased area.
Cost of providing power has resulted in
significant interest in power reduction of
non portable devices

Adiabatic logic
THE term adiabatic describe the thermodynamic
processes in which no energy exchange with the
environment, and therefore no dissipated energy loss.
Fully adiabatic operation of a circuit is an ideal
condition.
Adiabatic logic circuits reduce the energy dissipation
during switching process, and reuse some of energy by
recycling from the load capacitance.
For recycling, the adiabatic circuits use the constant
current source power supply and for reduce dissipation
it uses the trapezoidal or sinusoidal power supply
voltage

Basics of Adiabatic Circuits:

Conventional CMOS:

When PFET is Switched ON,

Energy from Source=CV2
Energy in Capacitor= CV2
Energy Lost = CV2 -> PFET
Q=CV, E=CV2
Vin = 0
Q=CV, E=CV2

When NFET is Switched,

Energy Drained= CV2
Energy Lost = CV2 -> NFET

itching event always dissipates energy equal to signal energy,

Basics of Adiabatic Circuits:

Adiabatic Charging:

The energy dissipation in Resistance R i

Since Ediss depends upon R, so by reducing the on resistance of PMOS

network the energy dissipation can be minimized.

 Ediss also depends upon the charging time T, If T>>

2RC then energy dissipation will be smaller than
the conventional CMOS .

The energy stored at output can be retrieved by

the reversing the current source direction during
discharging process instead of dissipation in NMOS
network. Hence adiabatic switching technique
offers the less energy dissipation in PMOS network
and reuses the stored energy in the output load
capacitance by reversing the current source
direction.

ADIABATIC LOGIC
FAMILIES

Popular Partially Adiabatic families

include the following:
1. Efficient Charge Recovery Logic (ECRL).
2. 2N-2N2P Adiabatic Logic.
3. Positive Feedback Adiabatic Logic
(PFAL).
4. NMOS Energy Recovery Logic (NERL).
5. Clocked Adiabatic Logic (CAL).
6. True Single-Phase Adiabatic Logic
(TSEL).

ADIABATIC LOGIC
FAMILIES
Some Fully adiabatic logic families
include
1. Pass Transistor Adiabatic Logic (PAL)
2. Split- Rail Charge Recovery Logic
(SCRL).
In a PARTIALLY ADIABATIC CIRCUIT, some
charge is allowed to be transferred to the ground,
while in a FULLY ADIABATIC CIRCUIT, all the
charge on the load capacitance is recovered by the
power supply.

ADIABATIC LOGIC
FAMILIES

Adiabatic system has:

Digital core: adiabatic gates
Generator of power clock signals
4-phase power clock for cascaded gates
Efficient generation essential for high
energy saving factor
Two of the most popular
Efficient Charge Recovery Logic (ECRL)
Positive Feedback Adiabatic Logic (PFAL)

Each power-clock cycle consists

of four intervals.
In the evaluate (E) interval, the
outputs are evaluated from the
stable input signals.
During the hold (H) interval,
outputs are kept stable for
supplying the subsequent gate
with a stable input signal.
Energy is recovered in the interval
called recover (R).
And for symmetry reasons a wait
(W) interval is inserted.

Efficient Charge Recovery Logic

(ECRL)

Scheme of the
four-phase powerclock

Efficient Charge Recovery Logic

(ECRL)

An ECRL buffer
and an exemplary
scheme of
the signals in the
gate in
operation

Schematic of a
static CMOS
inverter

Efficient Charge Recovery Logic

(ECRL)
Adiabatic Logic does not abruptly switch
from 0 to VDD (and vice versa), but a
voltage ramp is used to charge and
recover the energy from the output.
The gate consists of two cross-coupled
PMOS devices that are used to store the
information. The logic function is
constructed via two NMOS devices.
Cascaded gates are operated by a fourphase power-clock signal

Positive Feedback Adiabatic

Logic (PFAL)

Consists of:
Latch made of 2
cross-coupled
inverters
Logic function

ERCL vs PFAL
ERCL: less number of transistors
PFAL:
- Functional block parallel to PMOS
- less equivalent resistance
- less energy dissipated (R* C2 *
Vdd2/T)

Cons and Pros

Slower than conventional CMOS
Requires special power supply
Area (but we get function and its
complement)
+ Less Power if high switching
activity
or disconnect system from power
supply while idle (sleep transistors)

References

Teichmann, Philip; Adiabatic Logic; Springer; 2012

2.Vitnyi, P.; Time, space, and energy in reversible
computing; Proceedings of the 2nd conference on
Computing frontiers, ACM, 2005, 435-444
3.Pahlavan,B; Evaluation of Trends in Adiabatic Logic for
Low Power Design
http://cutler.eecs.berkeley.edu/classes/icdesign/ee241_s06/p
rojects/midterm/pahlavanghanadanskucha.pdf
4.Frank, M; Reversible Computing and Truly Adiabatic
Circuits: Truly Adiabatic Circuits: The Next Great Challenge
for Digital Engineering; 2006
5.Sanjay Kumar; Design Of Low Power Cmos Cell Structures
Based On Adiabatic Switching Principle; Master Thesis; 2009