Machine Cycles and Bus

Timings
Microprocessor includes
158 different instruction types.
Each instruction has two parts:
Operation code (known as opcode) and operand.

Assume that the instruction is stored in 2 Bytes

The Z80 has to perform three operations:
Read Byte 1 from the first memory location
Read Byte 2 from the next memory location
Send Data to port 10H

Machine Cycles and Bus

Timings

Instruction Cycle

the time required to complete the execution of an

instruction. The Z80 instruction cycle consists of
one to six machine cycles or one to six operations.

Machine Cycle
The time required to complete one operation of
accessing memory, accessing I/O, or acknowledging
an external request. This cycle may consist of three
to six T-states.

T-state
One subdivision of operation performed in one clock
period. These subdivisions are internal states
synchronized with the system clock and each Tstate is equal to one clock period.

Machine Cycles and

Control Signals

Opcode Fetch Machine

Cycle
AddressMachine
Code (M1)
Instruction
Comment
2002H

01000111 (47H)

Copy A into B

LD B, A

Opcode Fetch Machine

Cycle (M1)

The Timing of the Opcode

Fetch
Machine Cycle

The Timing of the Opcode

Fetch
Machine Cycle

Memory Read Machine

AddressMachine Cycle
Code
Instruction
Comment
2000H
00111110 (3EH)
LD A,9FH Load 9F in the
accumulator 2001H
10011111 (9FH)

The instruction consists of two bytes: Opcode

byte and Data byte.
The Z80 must first read these bytes from memory
Requires at least two machine cycles.
The first machine cycle is Opcode Fetch, and
the second machine cycle is Memory Read

Memory Read Machine

Cycle

Memory Read Machine

Cycle

Memory Write Machine

Cycle
H

23

50

Address
2003H
memory

Accumulator
9F

Machine Code
01110111 (77H)

Instruction

Comment

LD (HL),A Copy contents of A into

location, the address of which is

stored in HL

This is a one-byte instruction with two machine

cycles:
The first machine cycle is Opcode Fetch (Z80 fetches the
code 77H),
the second machine cycle is Memory Write (Z80 copies the
byte 9FH from the accumulator into the memory
location 2350H)

Memory Write Machine

Cycle

Memory Write Machine

Cycle

Memory
Interfacing

Interfacing Memory

An address should be placed

on the address lines.
The low-order address lines
are decoded by the internal
decoder of the memory chip,
and the addressed register is
identified.
The high-order address lines
should be decoded to
generate a Chip Select signal,
and the memory chip is
selected by asserting the
Chip Select (
) low.

Interfacing Memory
To read from the addressed register, the
should be asserted low to enable the
output buffer, and then the data byte
from the register will be placed on the
I/O lines.

To write into the addressed register, the

should be asserted low to enable the
input buffer, and then data bits from the
data lines are stored into the register.

How does the Z80 Read

from or Write into
Memory

Basic Concepts in Memory

Interfacing

Function of Interfacing :
To allow the microprocessor to read from
and write into a given register of a
memory chip
To perform these operations, the
microprocessor should
be able to select the chip
identify the register
enable the appropriate buffer.

Read from the Memory

Write into the Memory

register

Address Decoding
Identifying a register with a given address
We should be able to generate a unique pulse for that
address
goes low (active) only when the address on the
Using a gate :
address lines is F7H . No other address can
cause the output of the gate to go low. This
process is called decoding the address.

Using a decoder for address decoding (3-to

8 decoder):
3 input lines A0-A2 have 8 different logic
combinations from 000 to 111 each of
which can be identified by the
corresponding output line if enable lines are
active.
3 input lines enable only one output line
A3 A7 are control lines since the addresses

Example 1: Interfacing the

2764
EPROM
Used in
industry to
develop microprocessorbased products.
8k (8192 x 8) memory
chip with 8 data lines
Housed in a 28-pin
package.

Example 1: Interfacing the

2764 EPROM

What is the Memory Addresses Range (Memory Map of this chip)?

Absolute (full) memory address

Example 2: Interfacing the

CMOS 6116 Static R/W
This is a 2k static memory
chip
Memory
organized as 2048 x 8 format.

It has 11 address lines (A10A0),

8 data lines
3 control signals:

Example 2: Interfacing the

CMOS 6116 Static R/W
Memory

What is the addresses range? Assume A12

and A11 are do not care .

Address ranges may differ due to the do not care at A12 and A11
Assume A12 and A11 are zero

Ambiguous (partial) memory address

Example 2: Memory Address

Other addresses ofRange
this memory chip
8800H - 8FFFH
9000H - 97FFH
9800H 9FFFH
Entire memory address range: 8000H-9FFFH as if it is 8K memory
We have only 2K of memory occupying the memory space of 8K
Because of dont care lines each register can have 4 addresses, for
example, 8000H, 8800H, 9000H, and 9800H will select the same register
Duplicate range of memory space (8800H-9FFFH) cannot be used by any
other memory chip.

: Basic memory address range

Memory Map
The entire memory
addresses can range
from 0000H to
FFFFH.
Memory map is like
a pictorial
representation in
which memory
devices are located
in the entire range
of addresses.
Interfacing logic
defines the memory
map.

Example

After analysing the

address decoder for
memory address
ranges, memory map
can be found

Reading Assignment
Please Read
Chapter 3
Chapter 4

I/O Interfacing

Interfacing I/O Devices

I/O modes
SerialMode : Data entered or exited in serial
ParallelMode : Data entered or exited in parallel

Interfaced through:
Peripheral mapped I/O : Each device has a 8-bit
address and enabled by I/O related control signals
Memory mapped I/O : Each device has a 16-bit
address and enabled by memory related control
signals

The Z80 uses the instructions:

IN to read (input) data from an input device
and
OUT to write (send) data to an output device.

OUT Instruction Example

When the microprocessor reads and executes the

machine codes written at memory register 2050H
and 2051H, it will transfer (copy) the byte from the
accumulator to the LED port with address 07H and
display the byte.

Execution of OUT Instruction

The OUT has three machine
cycles:Timing
Opcode Fetch, Memory Read (port address),
and
and I/O Write

The Z80 reads the opcode and the

port address from memory in the
first two machine cycles and writes
into the port in the third cycle.

Execution of OUT Instruction

and Timing

Basic Concepts in Interfacing

Output Devices

Example 1: Interfacing
LEDs74LS373 Octal Latch
Hardware:

7475 Latch
4 D-Latches
2 enable lines

Latch followed by
tri-state buffer
Reduces loading on the
data bus at the output
8 latches instead of 4

Example 1: Interfacing
LEDs
Port address of the latch: 07H
When Q is high it can supply (source)
0.4 mA, and when it is low, it can sink
16 mA. Since LEDs require 10-15 mA
current to be illuminated, they are
connected to output of the latch.
When the input is high the LED is
turned on.

Instructions:
To display data for example, 97H at
this LED port instructions are:
LD A,97H
OUT (07H),A

Example 2: Using a
Seven-Segment LED as a
Display Device

IN Instruction - Example
IN instruction:Read (copy) data from such input
devices as switches, keyboard, and A/D data
converters.
Can read an input device and place the data into the
accumulator, Z80 registers, or memory registers.
Example:

IN Instruction - Example
First read the machine codes stored at locations
2065H and 2066H,
Read the switch positions at port 84H by enabling
the interfacing device of the port.
The data byte indicating switch positions from the
input port will be placed in the accumulator.

Execution of IN Instruction
andcycles:
Timing
The IN has three machine
Opcode Fetch,

Memory Read (port address), and

I/O Read
The Z80 reads the opcode and the port address from
memory in the first two machine cycles and reads
from the port in the third cycle. The first two
machine cycles are exactly the same as that of OUT
instruction.

Example : Interfacing Input

Interfacing device: 74LS244 tri-state octal buffer
switches
(two groups of four buffers) controlled by the
Port address of the buffer: 84H

active low
.
When it is low, input data appears on the output
lines, when it is high, the output goes to high
impedance state.

Example : Interfacing Input

switches
The address lines A4 and
A3 are not used by the decoding circuit;
the logic levels on these lines can be either 0 or 1.

Multiple port addresses: Ambiguous I/O address decoding

(Partial decoding)

Instructions:
To read data from the input port,
the instruction
IN A,(84H)
can be used.

Memory Interface Exercise

Solution

Instructions:
LD HL,(0100H)
LD A,L
LD (2000H),A
LD A,H
LD (2800H),A

I/O Interface Exercise

Solution

OUTPUT
PORT

Output port addresses:

80H, 90H, A0H, B0H, C0H, D0H, E0H, F0H
Input port addresses:
82H, 92H, A2H, B2H, C2H, D2H, E2H, F2H
Partial I/O address decoding

80H

INPUT
PORT

82H

Instructions:
IN A,(82H)
OUT (80H),A

Reading Assignment
Please Read
Chapter 5