Lecture Contents

Introduction
SRAM Overview
Novel SRAM bitcell
Test Chip Architecture
Summary

Introducti
on

6T SRAM

Bitcell
Design

Architectur
e

Summary

Memory Classification
Memory is classified by 4 major categories
Volatility, Access Speed, Capacity and Cost

Volatile

Introducti
on

6T SRAM

Bitcell
Design

Architectur
e

Non
Volatile

Summary

Motivation & Goal

Minimum energy point in digital
circuits is achieved at subthreshold
voltages
(Vdd < Vt).
Low-voltage operation of SRAM
memories in the subthreshold region
offers substantial power and energy
savings at the cost of speed.
This project focuses on the design and
implementation of a novel SRAM bitcell
for use in the subthreshold region.
Introducti
on

6T SRAM

Bitcell
Design

Architectur
e

Summary

SRAM OVERVIEW

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Overview
Bistability Principle (Q, QB)
Fast Access Speeds (read,
write)
Large Noise Margins
Prechargable Bitlines

Introductio
n

6T SRAM

Differential Read (Sense

Amp)
Differential Write
Large Area (6 transistors)
Power Consuming

Bitcell
Design

Architectur
e

Summary

Bistability Butterfly Curve

Positive feedback creates two stable points 1 and
0.
Regenerative property ensures a noisy cell
converges back to nominal values.

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

SRAM Read Access

1.
2.
3.
4.

Bitlines (BL, BL) are precharged to VDD

Wordline signal (WL) is asserted
One of the bitlines is pulled down toward GND.
Differential signal (BL-BL) is amplified to
accelerate the process.

>

M5

!
nt
i
ra
t
ns
o
C

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

SRAM Write Access

1. Bitlines are precharged to complementary
values.
2. Worldline signal (WL) is asserted.
3. Q is pulled down to GND while Q is driven to
VDD.

>

M4

!
nt
i
tr a
s
n
o
C

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

SRAM Subthreshold
Challenges
In general, ratioed digital circuits are more
likely to fail in subthreshold voltages.
6T Bitcells cannot operate below
600mV 700mV.
Read SNM problem - degraded read noise
margins decrease bitcell stability.
Write fails under 600mV due to the
increase of the pMOS drive in subthreshold.
Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

NOVEL 9T SRAM BITCELL

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

The Research Work

Numerous novel low-power SRAM
memories have been proposed in
recent years.
We studied and analyzed many of the
important proposals which include :
6T, 7T, 8T, 9T, 10T bitcells, Virtual VDD,
Virtual GND, DCVSL, Voltage Boost,
Read Buffer, Read Assist, Voltage Boost,
and more .
Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Brain Storming

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Major Achievements
Two innovative SRAM 9T bitcells, named PSRAM
and SFSRAM , aimed at eliminating static power
consumption and operated in the subthreshold
region were fully designed and analyzed.
Three types of 8-kb 40 nm SRAM test chips,
nicknamed
RAMBO, were designed for operation at 600mV
and below.
We are the first academic
research team in
Israel to fully design and
fabricate a
state-of-the-art 40nm CMOS
silicon chip.
Introductio
Bitcell
Architectur
6T SRAM
Summary
n

Design

Chip Design Workflow

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Standard 8T Schematic and

Layout
Schematic
Stick Diagram
of a of
standard
a standard
8T 8T
SRAM
SRAM bitcell
bitcell

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Pseudo SRAM (PSRAM)

Pseudo static behavior - A novel bitcell
mechanism disposes of both data node
charges while holding a logical 1.
Leakage current is practically eliminated
during this low-power standby mode.
Up to 3.75X less static power
consumption than a standard 8T
cell at 0.9V.
Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

PSRAM Write 1
Operation
CLK synchronizes write access

Write wordline (enable) is asserted

Q is driven to 1 and QB to 0
Q is discharged to during standby
WBL is driven to 1 and WBLB to 0

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

PSRAM Power Reduction

1.35X

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

SFSRAM (Supply Feedback

SRAM)
Enables subthreshold write with a
Virtual-VDD technique weakening the
Supply VDD during write operation.
A new approach for the design of the
Virtual-VDD scheme reduces periphery
and thus, reduces write power.
Operates at ultra-low voltages, down to
200mV.
Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Standard 8T Revisited
Schematic
Stick Diagram
of a of
standard
a standard
8T 8T
SRAM
SRAM bitcell
bitcell

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

SFSRAM Power Reduction

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

40NM TEST CHIP

Introductio
n

6T SRAM

Bitcell
Design

Architect
ure

Summary

Chip Architecture

8-kb Array
Read-Bitline division
Level Shifters
Row Decoder
Sense-Amps
Precharge Units
Write Drivers
BIST
Introductio
n

6T SRAM

Bitcell
Design

Architect
ure

Summary

40nm Test Chip - Periphery

Schematic of Sensing Unit + Up

Shifter

Introductio
n

Schematic of Write Driver

Schematic of WL Driver + Down

Bitcell
Architect
Shifter
6T SRAM
Design

ure

Summary

2.90
um

1.40
mm

Test Chip Top Level Layout

1.40 mm
Introductio
n

6T SRAM

1.40 um
Bitcell
Design

Architect
ure

Summary

Chip Timing Diagrams

M access is synchronized by a clock. Bitline Precharge, write driving and digital logic execute during the
phase
Introductio
Bitcell
Architect
and
read/write take place
during the low
phase.
6T SRAM
Summary
n
Design
ure

SUMMARY

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Summary
A fully functional 8-kb array was layed out
and designed for the 40nm lp TSMC
process.
SFSRAM Memory successfully operates at
subthreshold voltages - no additional
periphery required.
Additional power savings can be achieved
in the PSRAM with a majority bit algorithm.
Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Summary Continued
PSRAM consumes up to 3.75X less
static power than a standard 8T
We Are Thecell.
first academic
research team in Israel to fully
design and fabricate a
state-of-the-art 40nm chip.

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary

Questions??
Chocolate
Chip

Digital
Chip

Introductio
n

6T SRAM

Bitcell
Design

Architectur
e

Summary