Department of Electronics and

Telecommunication Engineering
A Seminar on

Floating point arithmetic unit

Implemented on FPGA using
VHDL
Guided by
Prof. H. M. Raza

Brief outline:
IEEE 754 format
Floating point unit
VHDL
FPGA
EDA Tools and softwares
Design of arithmetic units
Conclusion

Introduction to Floating Point IEEE 754

Standard
Established in 1985 by IEEE
It has mainly two format
Single Precision (32-bit)
Double Precision(64-bit)

IEEE 754 single precision format

1.M*

Mantissa (M) (M)

Mantissa

Conversion Examples

Consider 9.5 is to be converted in standard IEEE754 format.

9.5 can be represented in binary as 1001.10
After normalization 1.00110*
Biasing is to be done to exponent 1.00110*
Similarly -12.076 can be represented as:

9.5 =

0 10000010 00110000000000000000000

-12.076 =

1 10000010

10000010011011101110101

Conversion of IEEE754 to
decimal
1
1011 0110 01100000000000000000000

= 49539595901075456.0
= 4.9539595901075456

What is ALU?
It is Arithmetic and logical unit
In simple words any unit which
performs the required mathematical
computations

Limitations of basic ALU

It operates only on Integer values,
hence less precision.
When forced to be operated on
floating point numbers then it
results in slow operations and lags
in accuracy

Floating point arithmetic

unit
FPAU is a arithmetic unit which is
capable to compute the floating point
numbers (real numbers)
Floating-point operations are often
pipelined, which increases the speed
of operation.

What is FPGA?
It is a semiconductor device that can
be programmed after manufacturing.
The FPGA-architecture consists of
many logic modules, which are
placed in an array-structure

FPGA architecture

Significant characteristics for the

FPGA-architecture
Array of logic-modules
Different logic-modules possible
Routing-channels physically exits
between logic-modules
Every logic-module can be
interconnected to any other logicmodul or I/O-module

Overview of VHDL
VHDL stands for Very High Speed
Integrated Circuit Hardware
Description Language
VHDL is widely used to model digital
systems
VHDL was originated in early 1980s

VHDL features
Structural Specification
Support for Design Hierarchy
Library Support
Support for Concurrent and Sequential
Statements
Type Declaration
Use of subprograms

Design flow
The design file is written in VHDL language
with the extension .vhd and often named as
its ENTITYs name.

The major steps in design flow are:

Compilation
Optimization
Place-and-route

VHDL Constructs

Entity definition
Architecture definition
Configuration
Process
Subprogram
Package
A VHDL design can be broken into multiple files. Each file contains entity and
architecture definitions, or packages.

VHDL Code Structure

Entity Declaration
Defines input/output ports

Architecture Declaration
Defines what the component does
Variables,
Signals, Constants defines

Component Mapping
Interconnects previously defined
components/entities.

Different modeling schemes in VHDL

Behavioral
defines outputs as function of input
Algorithms

but no implementation

Structural
Implements behavior by connecting
components
with known behavior

Example
entity andgate is
Port ( a : in
b : in
c : out

STD_LOGIC;

STD_LOGIC;
STD_LOGIC);

end andgate;
architecture Behavioral of andgate is
Begin
c <= a AND b;
end Behavioral;

EDA tools and softwares

used
Xilinx ISE design suit 14.7

This software is used to synthesize and simulate the VHDL

code developed.
Target device: Atlys Spartan-6 Academic

Development Kit
Spartan-6 XC6SLX45 FPGA
6,822 Spartan-6 logic slices , 43,661 Spartan-6 logic cells
Integrated Memory Controller Block (MCB)
2,088 Kbits of block RAM

Design and implementation of FPAU

In top-down design approach FPAU is
designed for four arithmetic modules,
addition, subtraction, multiplication
and division.
Selection of any of the above functions
in done with the operation code (Op)

Block diagram of FPAU

Input output information

A,B : input operands
Op : input operation code
Clk : input clock
R : Output Result
Op(

Op(0

1)
0

)
0

Function of Operation Code(Op)

0
1

Operation
Addition
Subtraction

Multiplication

Division

Algorithm for
addition/subtraction
Step 1: Take difference of two
exponents. Take the larger
exponent as the tentative
exponent of the result.

Step 2: Shift the Mantissa of the

number with the smaller
exponent, right through a number
of bit positions that is equal to the
difference of exponents.

Step 3: Add/subtract the two

Mantissas as per sign bits and
instruction and take the result of
two as the tentative mantissa of
result.
Step 4: Normalization of

Algorithm for
Multiplication

Step 1: Add two exponents. Take

the result tentative exponent of
the result.

Step 2: Multiply two mantissas

Step 3: Normalization
Step 4: set the sign bit

Block diagram of
multiplier/divider

RESULTS

Synthesis summary

Inferred

Multiplier(s).
Inferred 31

Inferred

2 Comparator(s).

Inferred 141 Multiplexer(s).

Adder/Subtractor(s).
Inferred 256 D-type flip-

Timing Summary
flop(s).
Minimum period: 7.936ns (Maximum Frequency:
126.004MHz)

Simulation results while performing

addition

Simulation results while performing

multiplication

Conclusion
Synthesis

of

the

Floating

Point

Unit

targeted for the FPGA device had been done

using Xilinx-ISE design suit 14.7. Synthesis
result revels approximate 05% resource
utilization

i.e.

404

slices

(202

CLBs).

Correspondingly the logic verification of FPU

is done using ModelSim DE edition.