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Dekkers Algo
Dekkers Algo
A Tutorial
By Sarita Adve & Kourosh Gharachorloo
Review by Jim Larson
Outline
Optimizations on a Uniprocessor
Conclusion
Outline
Optimizations on a Uniprocessor
Conclusion
Outline
Optimizations on a Uniprocessor
Conclusion
Flag1 = 1
Write Buffering
Flag2 = 1
Flag1 = 1
Write Buffering
Flag2 = 1
Flag1 = 1
Write Buffering
STALL!
Flag1 =
0
Flag2 =
0
Flag2 = 1
Flag1 = 1
Write Buffering
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag2 = 1
Write Buffering
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Outline
Optimizations on a Uniprocessor
Conclusion
Understanding Ordering
Program Order
Compiled Order
Interleaving Order
Execution Order
Reordering
Caused by Processor
Caused by Compilers
Outline
Conclusion
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag1 = 1
Flag1 =
0
Flag2 =
0
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag1 = 1
Flag1 =
0
Flag2 =
0
Flag2 = 1
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag1 = 1
Flag1 =
0
Flag2 =
0
Flag2 = 1
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag1 = 1
Flag1 =
0
Flag2 =
0
Flag2 = 1
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag1 =
0
Flag2 =
0
Flag2 = 1
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
Flag1 =
0
Flag2 =
0
Flag2 = 1
Multiprocessor Case
Rule: If a WRITE is issued, buffer it and keep executing
Unless: there is a READ from the same location (subsequent
WRITEs don't matter), then wait for the WRITE to complete.
What happens on a
Processor stays on that
Processor
Flag1 = 1
Flag1 =
0
Flag2 =
0
Flag2 = 1
WY
RY
RX
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RY WY
RY RX
WY RY
RX RY
WY RX
RX WY
WX WY
WX RX
WX RY
WX RY
WX RX
WX WY
WY WX
RX WX
RY WX
RY WX
RX WX
WY WX
WY RX
RX WY
RY RX
RY WY
RX RY
WY RY
RX
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RX
WY
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RX
WY
RX
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WY
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WY
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WY
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WY
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RY
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WX
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WX
WX
Head =
0
Data =
0
Memory Interconnect
Head =
0
Data =
0
Memory
Interconnect
Data
= 2000
Head =
0
Data =
0
Head =
1
Data =
0
Head =
1
Data =
0
Head =
1
Data =
0
Head =
1
Data =
2000
Head =
0
Data = 0
Head =
0
Data = 0
Head =
0
Data = 0
Head =
0
Data = 0
Head =
0
Data =
2000
Head =
1
Data =
2000
Head =
1
Data =
2000
Head =
1
Data =
2000
RY
WY
RX
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RY
RY
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WY
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RY
RY
WY
RX
WY
RX
RY
RY
WY
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WY
RX
WX
WX
WX
WX
WX
WX
WY
RX
RY
RY
RX
WY
WY
RX
RY
RY
RX
WY
WY
RX
RY
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RX
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RX
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WY
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RX
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WY
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RX
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WY
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RX
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RY
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RY
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RY
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WY
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RY
RY
WY
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RX
WX
WX
WX
WX
WX
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RY
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RX
WY
WY
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RY
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RX
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RY
RY
RX
WY
WY
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RY
RY
RX
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RY
RX
WY
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WY
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RY
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WX
WX
WX
Outline
Optimizations on a Uniprocessor
Conclusion
?????
?????
Cache Coherence
Cache Coherence
Cache Coherence
Cache Coherence
Barrier Instructions
Barrier Instructions
Barrier Instructions
WY
>>Fence<<
RX
Fence: WX < RY
Fence: WY < RX
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RX
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RX
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RY
WX
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WX
WX
Flag1 =
0
Flag2 =
0
Flag1 =
0
Flag2 =
0
Flag2 = 1
Flag1 =
1
Flag2 =
0
Flag2 = 1
Flag2 = 1
Flag2 = 1
RY
>>Fence<<
RX
Fence: RY < RX
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WY
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WY
RX
WY
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RY
RX
WY
RX
WY
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RY
WX
WX
WX
WX
WX
WX
Memory Interconnect
Head =
0
Data =
0
Memory Interconnect
Head =
0
Data =
0
Memory Interconnect
Head =
0
Data =
2000
Head =
1
Data =
2000
Head =
1
Data =
2000
Words of Advice?
Programmer's View
Outline
Optimizations on a Uniprocessor
Conclusion
Conclusion
Conclusion
Conclusion
Conclusion
References