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Lecture 10
Lecture 10
Power Dissipation
Outline
Leakage
Leaking diodes and transistors
= C V 2 n N
L
dd
n N
lim
N N
P av g = 0 1 C V dd 2 f clk
L
(1 p A p B ) p A p B
(1 p A )(1 p B )[1 (1 p A )(1 p B )]
[1 ( p A p B 2 p A p B )]( p A p B 2 p A p B )
Istat
Vin =5V
Vout
CL
Wasted energy
Not a function of switching frequency
Should be
avoided in almost all cases
Solutions
MTCMOS
Dual Vt
Dual Vt domino logic
Adaptive Body Bias
Transistor stacking
Metrics
Power Delay product
Energy Delay Product
Average energy per instruction x average inter
instruction delay
Cunit_area
Capacitance per unit area
Conclusion
Power dissipation is unavoidable especially as
technology scales down
Techniques must be devised to reduce power dissipation
Techniques must be devised to accurately estimate the
power dissipation
Estimation and modeling of the sources of power
dissipation for simulation purposes