Plaminimization 140207073226 Phpapp02

PLA MINIMIZATION FOLDING
&
PLA TESTING
Dr. Y. NARASIMHA MURTHY. Ph.D

SRI SAIBABA NATIONAL COLLEGE
(Autonomous)
ANANTAPUR-515001-A.P
yayavaram@yahoo.com
10/18/15
Dr.Y.Narasimha Murthy .Ph.D
Prologue- PLA
PLA(Programmable Logic Array) is a LSI
based
(Large Scale Integration ) device and its
Field programmable version is called FPLA.
PLA is an array logic device with matrix
like structure which is designed to
implement random logic expressions in sum
of Product form(SOP).
10/18/15
Contd..
The Programmable Logic Array (PLA) has a

very special structure for the design of both
combinational and sequential logic.
They have been extensively used in

integrated circuit design, especially in
controller implementations.
A PLA consists of a group of rows (carrying
each one a product term) and
columns
(corresponding to inputs and outputs). A logic
gate can be located at each intersection of a
row with a column
10/18/15
Contd..
PLAs are used to implement control units
of CPUs, arithmetic circuits, decoders and
finite state machines (FSMs).
PLAs can also be used to implement the
"IF-THEN ELSE conditional statement"
present in programs written using
hardware description languages.
They have been used in the design of an
entire Microprocessor, terminal control
units, ALU chips and other logic systems.
10/18/15
Structure of a PLA
PLAs are used to implement logic functions that

are given in the Sum-of-Products (SOP) form.
A PLA is made up of two programmable planes,
called the AND-plane and the OR-plane.
For every input signal, there is one column in the
AND-plane, and for every output signal, there is
a column in the OR-plane.
Separate columns are assigned to the

complement and the un-complement input
literals in the AND plane
10/18/15
Diagram-PLA
10/18/15
Schematic-BCD to Gray code converter
10/18/15
ROM &PLA
The internal organization of the PLA is
different from that of the ROM.
ROM consists of a decoder at the input while it
is replaced with an AND array which realizes
selected product terms of the input variables.
The basic difference is PLA implements a sumof-products expression, while a ROM directly
implements a truth table.
10/18/15
PLA- OPTIMIZATION
The major disadvantage of the PLA is that
most practical logic problems leave much PLA
area unused.
A straight forward physical design results into
a significant waste of silicon area, which is
undesirable.
Also, speed and power become critical
parameters as the size of the PLA increases
10/18/15
Contd..
The gate capacitances of the input signals

carried by long poly-silicon lines become the
key factor in determining the timing
(speed)performance.
In moderate to large PLAs, the poly-silicon
resistance becomes as important factor as the
capacitance.
The signal is degraded with the large resistance added

to the line, no matter how large the drivers are.
Further, if the PLA becomes large, the width of the
power and the ground lines should also be increased
to avoid possible metal
migration.
10/18/15
10
Contd..
Due to the regular structure the PLA takes
more area (space) when implemented in a
VLSI chip than the Gate or Standard cell
circuits.
To accommodate all components and
modules with in a small area (for
area efficient design) two important
operations are used.
One is the Minimization and the other
is the Folding of PLAs
10/18/15
11
Contd..
This minimization techniques are based on

Boolean minimization algorithms , which
remove redundant product terms and inturn
decreases the PLA area.
In the minimization process the functions
being implemented are reduced without
changing the input/output relationship, so
that the original PLA can be transformed
into a smaller one.
10/18/15
12
Boolean Minimization Techniques

One of the Boolean minimization techniques used is
to remove redundant product terms in the
personality matrix of a PLA and there by removing
the rows that implement these terms.
Another Boolean minimization technique is to

determine if a term xf can be replaced by a term
f, where f is the product of some variables other
than x and covers more min-terms than does xf.
This technique is called raising of terms .
10/18/15
13
Contd..
With the advancements in VLSI ,the problem of
minimization has become more cumbersome, due
to increase in the number of variables.
Hence most of the classical methods
have become almost outdated.
The first cube based algorithm MINI
was
developed at IBM by Hong et al in 1974.
Most extensively used PLA minimizer currently
available is ESPRESSO II ,developed at the
university of California-Berkeley by Brayton et al.
10/18/15
14
Contd..
The McBoole logic minimizer developed at McGill
university by Dagenais et al is based on the QuineMcCluskey philosophy and generates all the prime
cubes.
Another better multiple-output minimization
algorithm than ESPRESSO II and McBoole in
many PLAs has been developed at IISc,
Bngalore,India by Gurunath and Biswas in 1989.
This algorithm is based on switching theoretic
concepts and is a fast technique for the
determination of essential prime cubes only.
10/18/15
15
PLA Folding
Folding
is
a
technology-independent,
topological minimization technique, developed
for array structures , that attempts to place two
or more input/output (product term) signals
together so that they can share the same
physical column (row).
It does not change the implementation of the
logic in any manner, but reduces the number of
columns and rows, and consequently reduces
the area of the PLA.
10/18/15
16
Simple folding
When a pair of inputs or outputs share the
same column or row, respectively. It is
assumed that the input lines and the output
lines are either on the upper or lower sides of
the columns thus, there no intersections
between folded lines.
Most often, the input and output lines are

folded in the AND and OR matrix,
respectively, due to electrical and physical
constraints.
10/18/15
17
Multiple folding
It is a more general technique where the input
and output lines are folded as much as possible
to minimize the number of columns,
respectively rows, in AND and OR matrices.
This method reduces the area. However,
routing of the input and output lines is more
complicated, and another metal or poly-silicon
layer may be required.
Therefore, multiple folding is efficient when the PLA
is a component of a large system where several metal
or poly-silicon layers are already required
10/18/15
18
Contd
Bipartite folding is a special example of
simple folding where column breaks between
two parts in the same column must occur at the
same horizontal level in either the AND or
OR-matrix.
Constrained folding is a restricted folding
where some constrains such as the order and
place of lines are given and accommodated
with other folding
10/18/15
19
Contd..
It has been shown that PLA folding problems are
NP-complete and the number of possible solutions
approximates c! or r!, were c and r are the number of
columns and rows in the initial PLA, respectively.
As the number of inputs and outputs is very large in
recent modern PLAs ,its not possible to implement
these algorithms manually.
Hence the procedure of folding is automatized, and
many computer based (CAD tools) algorithms have
been proposed
10/18/15
20
Column Folding
Column folding is the sharing of a single physical
column by two or more columns (input/output
signals) of a PLA.
Column folding is said to be simple if utmost two
signals (logical columns) share a single physical
column.
It is called multiple if more than two columns can
share a single column.
Column folding can be obtained by permuting

the rows of the PLA as shown in the next slide.
10/18/15
21
Column folding
(a)Original
PLA
10/18/15
(b).Row Permuted PLA
22
Column folding can be obtained by permuting

the rows of the PLA. For example, in slide (a),
no column folding is evident.
However, from the given representation of the
PLA, if the rows are permuted so that r4, r2, rl,
r5, and r3 are in order, then it is possible to
fold and place the column a above the column
b. This row-permuted PLA is shown in slide
(b).
10/18/15
23
Contd..
From the previous slide it is clear that column

folding introduces a restriction on the order of
the rows.
More specifically, if column x is folded and
placed above column y, then all the rows that
receive the signal x must be placed above
those rows that use the signal y.
For example, in slide (b), to fold column a
above b, rows r4 and r2 should be placed
above rl , r5 and r3.
10/18/15
24
Contd..
The restrictions imposed on the order of rows

by one set of folded column signals might
conflict with the row ordering desired by
another set of folded columns.
Such conflicts on row orderings along with
some other conditions make column folding an
NP-complete optimization problem.
An ordering of rows is termed as optimal. if

it needs to the maximal folding of columns
10/18/15
25
Row Folding
Row folding is defined as the sharing of a
single physical row by two or more product
terms (logical rows) of a PLA.
Row folding is called simple if only two rows
share a single row and is called multiple if
more than two rows share a single row.
Row folding is more complex than column
folding, due to the fact that rows interact with
both the input and output columns.
10/18/15
26
Row-Folding-Example
10/18/15
27
Contd..
In order that two rows can be folded together, it is
necessary that the input columns feeding one row
be separated from those that feed the other by the
output columns. Such separation segments the
PLA.
There are two ways to segment PLAs for simple
row folding.
One, that splits the original AND-plane resulting
in the AND-OR AND structure.
The other that yields the OR-AND-OR structure.
10/18/15
28
Contd..
The PLA in the AND-OR-AND form, consists
of two AND-planes (the left and the right) and
an OR-plane between these two planes.
The OR-AND-OR PLA consists of two ORplanes (the left and the right) on either side of
an AND-plane.
In both cases, a row belonging solely to the left
(AND- or OR-) plane can be folded only with a
row belonging solely to the right (AND or
OR-) plane.
10/18/15
29
Contd..
A multiple row-folded PLA consists of a

sequence of alternating AND- and OR-planes.
Row folding can be achieved by segmenting
the PLA planes and then permuting the
columns appropriately.
10/18/15
30
TESTING-TESTABILITY
The concepts of fault modeling ,diagnosis
,testing and fault tolerance of digital circuits
have become very important research topics
for logic designers during the last decade.
With the developments in VLSI technology,
there is a drastic increase in the number of
components on a single chip and as a result
of increase in the chip density ,the
probability of fault occurring also
increased.
10/18/15
31
Contd..
The purpose of testing is to know the faults in
a system responsible for the degradation of the
performance and for unwanted effects in terms
of time and power etc.
It also helps to know whether the
manufactured chip meets the expected
specifications.
Among the various tests Functional tests,
Diagnostic tests and Parametric tests are very
important.
10/18/15
32
Types of Faults
There are different types of faults in digital

circuits. A Fault in a circuit is defined as the
physical defect of one or more components of
the circuit. Faults can be either permanent or
temporary. Permanent faults are caused by the
breaking or wearing out of components.
Permanent faults are also called Hard and
Solid faults.
Temporary faults are known as soft faults .The
faults that occur only certain intervals of time
are either transient or intermittent faults.
10/18/15
33
Fault Modeling
Fault models are analyzable approximations of

defects and are essential for a test methodology
and identifies targets for testing.
There are three important models of
logical faults. They are
Stuck-at faults
Bridging Faults and
Delay Faults.
10/18/15
34
Stuck-At Fault
The most common model used for logical
faults is the single Stuck-at Fault.
It assumes that a fault in a logic gate results in
one of its inputs or the output is fixed at either
a logic 0 (stuck-at-0) or at logic 1 (stuck-at-1).
Stuck-at-0 and stuck-at-l faults are denoted
by abbreviations s-a-0 and s-a-1, respectively.
10/18/15
35
Contd..
As an example let us consider a NAND Gate shown

in the slide ,whose input A is s-a-1.
The NAND gate perceives the A input as a logic 1
irrespective of the logic value placed on the input.
For example, the output of the NAND gate is 0 for
the input pattern A=0 and B=1, when input A is s-a1.
In the absence of the fault, the output will be 1.
Thus, AB=01 can be considered as the test for the A
input s-a-l, since there is a difference between the
output of the fault-free and faulty gate.
10/18/15
36
Contd..
The single stuck-at fault model is often referred to as the
classical fault model and offers a good representation for
the most common types of defects for e.g., short
circuits(shorts ) and open circuits (opens) in many
technologies.
The stuck-at model is also used to represent
multiple faults in circuits. In a multiple stuck-at
fault, it is assumed that more than one signal
line in the circuit are stuck at logic 1 or logic 0.
In other words, a group of stuck-at faults exist
in the circuit at the same time.
10/18/15
37
Contd..
The stuck-at model is not very effective in
accounting for all faults in very large scale
integrated (VLSI), circuits which mainly uses
CMOS technology.
Faults in CMOS circuits do not necessarily
produce logical faults that can be described as
stuck-at faults.
Some times the faults may be due to
faults in transistors also.
10/18/15
38
Bridging Faults
Bridging faults are an important class of
permanent faults that cannot be modeled as
stuck-at faults.
A bridging fault is said to have occurred when
two or more signal lines in a circuit are
connected accidently together.
Bridging faults at the gate level have
been classified into three types:
input bridging and feedback bridging
and non-feedback bridging.
10/18/15
39
Contd..
An input bridging fault corresponds to the shorting
of a certain number of primary input lines.
A feedback bridging fault results if there is a short
between an output and input line.
A feedback bridging fault may cause a circuit to
oscillate, or it may convert it into a sequential
circuit.
Bridging faults in a transistor-level circuit may
occur between the terminals of a transistor or
between two or more signal lines.
10/18/15
40
Contd..
A short between two lines, as indicated by the

dotted line in the diagram will change the
function of the circuit. The effect of bridging
among the terminals of transistors is technologydependent .
10/18/15
41
Contd..
A non-feedback bridging fault identifies a

bridging fault that does not belong to either of
the above types.
If bridging between any s lines in a circuit
are considered ,the number of single bridging
faults alone will be ( n/s)! and the number of
multiple bridging faults will be very high.
10/18/15
42
Delay Faults
Smaller defects, which are likely to cause

partial open or short in a circuit, have a higher
probability of occurrence due to the statistical
variations in the manufacturing process.
These defects result in the failure of a circuit to
meet its timing specifications without any
alteration of the logic function of the circuit.
A small defect may delay the transition of a
signal on a line either from 0 to 1, or vice versa.
This type of malfunction is modeled by a delay
fault.
10/18/15
43
Contd..
The delay faults are two types.They are
(a) Gate delay fault and (b)Path delay fault.
Gate delay faults have been used to model
defects that cause the actual propagation delay
of a faulty gate to exceed its specified worst
case value.
For example, if the specified worst case
propagation delay of a gate is x units and the
actual delay is x+x units, then the gate is said to
have a delay fault of size x.
10/18/15
44
Contd..
The main deficiency of the gate delay fault
model is that it can only be used to model
isolated defects, not distributed defects, for
example, several small delay defects
The path delay fault model can be used to
model isolated as well as distributed defects. In
this model, a fault is assumed to have occurred
if the propagation delay along a path in the
circuit under test exceeds the specified limit.
10/18/15
45
Transition and Intermittent faults

The transition and Intermittent faults are
considered as Temporary faults.
In digital circuits a major part of the
malfunctioning is due to the temporary faults
and these faults are always difficult to detect
and isolate.
Transient faults are non-recurring temporary
faults that caused by power supply fluctuations
or exposure of the circuit to certain external
radiation(like -particle radiation).
10/18/15
46
Contd..
Intermittent faults occur due to loose connections
, partially defective components or poor designs.
They are recurring faults that appear on regular
basis.
The intermittent faults that occur due to
deteriorating or aging components may
eventually become permanent.
Some intermittent faults may also occur due to
environmental conditions such as temperature,
humidity ,vibration etc.
10/18/15
47
Contd..
The occurance of intermittent faults depends
on how well the system is protected from its
physical environment through shielding,
filtering ,cooling etc.
An intermittent fault in a circuit causes
malfunction of the circuit only if it is active , if
it is inactive ,the circuit operates correctly.
A circuit is said to be in a fault active state if a
fault present in the circuit is active and it is
said to be in the fault-not-active state if a fault
is present but inactive
10/18/15
48
PLA TESTING
Programmable logic arrays (PLAs) are used to
implement any Boolean function. Hence , they
have become a popular device in the
realization of both combinational and
sequential logic circuits and are used
extensively in VLSI designs and as LSI
devices on printed circuit boards.
The widespread application of PLAs makes
PLA testing an important issue. Though PLAs
offer many advantages, they also present new
testing problems
10/18/15
49
Test Generation Algorithms for PLAs

Since conventional test generation methods are
not suitable for PLAs, several ad hoc test
generation approaches have been developed.
It is a fact that a PLA's regular structure leads
to more efficient test generation and fault
simulation
algorithms
than
for
random logic .
10/18/15
50
Testable PLA Designs

As the size of PLAs increase, more test
patterns have to be generated and stored.
Sophisticated automatic test equipment is
needed to execute the test process. Hence
stored-pattern testing becomes a timeconsuming and expensive task.
To solve this problem, several hardwareoriented approaches have been developed that
add extra built-in test (BIT) circuitry to the
original PLA such that the modified PLA can
be easily tested.
10/18/15
51
Concurrent Testable PLAs

A PLA's regular memory-like structure
suggests the application of special coding for
either concurrent or off-line fault detection.
To test a PLA concurrently, i.e., during normal
operation, requires that during fault-free
operation only one product line can be
activated by any input vector.
Concurrent Error Detection technique was
proposed by Khakbaz and McCluskey.
10/18/15
52
Concurrent testable PLA design
10/18/15
53
Contd..
The testable PLA, shown in earlier slide has
three checkers.
C1 is a totally self-checking (TSC) l-out-of-m
checker on all product lines and detects any fault
that destroys the non-concurrent property, such
as a product line stuck at 1(0), or any missing
and/or extra cross point in the AND array.
C2 is a TSC two-rail checker that tests all single
stuck-at faults on the bit lines and input
decoders. C3 is an output-code checker.
10/18/15
54
Contd..
C3 is an output-code checker. Its complexity
depends on how the outputs are coded.
The simplest code makes all output patterns
have even (odd) parity. Here, only one extra
output line needs to be added, and C 3 would be
a parity checker.
In general, C3 is not a TSC checker and may
not be fully tested during normal operation,
since the inputs to C3 are basically the PLA's
outputs that are not directly controllable.
10/18/15
55
Contd..
Testing occurs concurrently with normal
operation.
Most errors are caught by one of the three
checkers. However, the circuit is not totally selfchecking.
Therefore off-line testing is still needed to ensure
a high fault coverage.
This technique combines concurrent error

detection with off-line testing by using the
same added circuits for both modes of testing.
10/18/15
56
Parity Testable PLAs

The most popular code for PLA testing is the
parity code.
Since PLAs have a regular array structure, it is
possible to design a PLA so that it can be
tested by a small set of deterministic tests that
are function-independent, i.e., independent of
the personality matrix.
This is possible because of two important
concepts given in the next slide.
10/18/15
57
Contd..
Let N, be the number of used cross points on
bit line bi. One can add an extra product line
and make connections to it such that every bit
line has an even(odd) number of connections
with product lines.
Then any single cross-point fault on bi
changes the parity of Ni.
The same is true for output lines. Therefore
single cross point faults can be detected by
parity checking on these lines.
10/18/15
58
Contd..
To test a PLA easily, it must be possible to
control individually each bit and product line,
and sensitize each product line through the OR
array.
To obtain more efficient testable PLA designs,
some researchers have focused on reducing
area overhead and/or increasing fault coverage.
This can be done using the idea of parity
compression
10/18/15
59
Signature-Testable PLAs
Signature analysis is a simple and effective
way for testing digital systems, and several
self-testing PLA designs using this concept
have been proposed.
In these approaches ,a set of input patterns is
applied and the results are compressed to
generate a signature , which, when compared
with a known correct value, determines
whether the PLA is faulty or not.
10/18/15
60
Partitioning and Testing of PLAs
Testing becomes more complex as the size of

the PLA increases.
A common strategy for dealing with large
complex PLAs is that of divide and conquer.
This principle has also been applied to the
design of testable PLAs.
10/18/15
61
References
This lecture is totally incomplete with out the
help of the following references. My heartfelt
thanks to these authors.
1. Partition Based Algorithms for PLA
Folding By .Karthikeyan Kannappan.
2. Digital systems Testing and TestableDesign
By Miron Abramovici.
3. Logic Design Theory- N. Biswas.
10/18/15
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PLA MINIMIZATION FOLDING

Dr. Y. NARASIMHA MURTHY. Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

The Programmable Logic Array (PLA) has a

They have been extensively used in

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

PLAs are used to implement logic functions that

Separate columns are assigned to the

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Schematic-BCD to Gray code converter

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

The gate capacitances of the input signals

The signal is degraded with the large resistance added

Dr.Y.Narasimha Murthy .Ph.D

This minimization techniques are based on

Dr.Y.Narasimha Murthy .Ph.D

Boolean Minimization Techniques

Another Boolean minimization technique is to

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Most often, the input and output lines are

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Column folding can be obtained by permuting

Dr.Y.Narasimha Murthy .Ph.D

(b).Row Permuted PLA

Dr.Y.Narasimha Murthy .Ph.D

Column folding can be obtained by permuting

Dr.Y.Narasimha Murthy .Ph.D

From the previous slide it is clear that column

Dr.Y.Narasimha Murthy .Ph.D

The restrictions imposed on the order of rows

An ordering of rows is termed as optimal. if

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

A multiple row-folded PLA consists of a

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

There are different types of faults in digital

Dr.Y.Narasimha Murthy .Ph.D

Fault models are analyzable approximations of

Dr.Y.Narasimha Murthy .Ph.D

Dr.Y.Narasimha Murthy .Ph.D

As an example let us consider a NAND Gate shown

Dr.Y.Narasimha Murthy .Ph.D