Welcome

Our presentation
Under the supervisor
of

Md. Mizanur Rahman

Assistant Professor
ECE Discipline
Khulna University
Khulna
 Submitted By
A.K.M. Touhidur Rahman
ECE Discipline
Khulna University
Khulna

Roll no. 090918

 Discussion on
Field effect transistor (FET): the junction field effect transistor (JFET),
JFET operations and characteristics, pinch off voltage
and the behavior of pinch of region, biasing the FETs, FET as a VVR.
 Field Effect Transistors
Introduction:
A field effect transistor (FET) is a unipolar device, conducting a current using
only one kind of charge carrier. If based on an N-type slab of semiconductor, the
carriers are electrons. Conversely, a P-type based device uses only holes.

Differences BJT and FET:

FET’s are voltage controlled devices as depicted in fig-01(a) whereas BJT’s are
current controlled devices as shown in fig-02.
FET’s also have a higher input impedance, but BJT’s have higher gains.
FET’s are less sensitive to temperature variations and more easily integrated on
IC’s.
FET’s are also generally more static sensitive than BJT’s.
 IC ID
(Control current )IC

Control voltage )VGS

(a) (b)

Fig-01: (a) Current-controlled and (b) voltage-controlled amplifiers.

Types of FET:

Two main types of FET:

- JFET –Junction field effects transistor
- MOSFET – Metal oxide semiconductor field effect transistor
- D-MOSFET ~ Depletion MOSFET
- E-MOSFET ~ Enhancement MOSFET
 Construction of FETS:
3 type of FET will are given below;
Junction Field Effect Transistor (JFET)
i) n-channel
ii) p-channel
Depletion-type MOSFET
i) n-channel
ii) p-channel
Enhancement-type MOSFET
i) n-channel
ii) p-channel

Basic structure of FETS:

In addition to the channel, a JFET contains two ohmic contacts: the
source and the drain.
The JFET will conduct current equally well in either direction and the
source and drain leads are usually interchangeable.
 Construction and characteristics of JFET

N-channel JFET:
• N-channel device will appear as the prominent
device with paragraph and section devoted to the
impact of using a p-channel.
• Major part of structure is n-type material.
• Top of the n-type channel is connected through
an ohmic contact to a terminal referred to as the
drain (D)
• The lower end-connected through an ohmic
contact to a terminal referred as source (S)
• P-type materials are connected together and to
the gate (G) terminal.
• JFET has two p-n junctions under no-bias
conditions.
• JFET operation can be compared to a water spigot:

• The source of water pressure – accumulated electrons at the negative pole of the
applied voltage from Drain to Source
• The drain of water – electron deficiency (or holes) at the positive pole of the
applied voltage from Drain to Source.
• The control of flow of water – Gate voltage that controls the width of the n-channel,
which in turn controls the flow of electrons in the n-channel from source to drain.
 JFET n-CHANNEL Operating Characteristics

There are three basic operating conditions for a JFET:

A. VGS = 0, VDS increasing to some positive value

B. VGS < 0, VDS at some positive value
C. Voltage-Controlled Resistor
 VGS = 0, VDS increasing to some positive value

Three things happen when VGS = 0 and VDS

is increased from 0 to a more positive
voltage:
 the depletion region between p-gate and n-
channel increases as electrons from n-
channel combine with holes from p-gate.
 increasing the depletion region, decreases
the size of the n-channel which increases the
resistance of the n-channel.
 But even though the n-channel resistance is
increasing, the current (ID) from Source to
Drain through the n-channel is increasing.
This is because VDS is increasing.
 The flow of charge is relatively uninhibited and limited solely by the
resistance of the n-channel between drain and source.
 The depletion region is wider near the top
of both p-type materials.
 ID will establish the voltage level through
the channel.
 The result: upper region of the p-type
material will be reversed biased by about 1.5V
with the lower region only reversed biased by
0.5V (greater applied reverse bias, the wider
depletion region).
IG=0A  p-n junction is reverse-biased for
the length of the channel results in a gate
current of zero amperes.
As the VDS is increased from 0 to a few volts,
the current will increase as determined by Ohm’s Law.
VDS increase and approaches a level referred to as Vp, the depletion region will widen,
causing reduction in the channel width. (p large, n small).
Reduced part of conduction causes the resistance to increase.
If VDS is increased to a level where it appears that the 2 depletion regions would touch
(pinch-off)
 Vp = pinch off voltage.
 ID maintain the saturation level defined as IDSS
 Once the VDS > VP, the JFET has the
characteristics of a current source.
 As shown in figure, the current is fixed at ID =
IDSS, the voltage VDS (for level >Vp) is
determined by the applied load.
 IDSS is derived from the fact that it is the drain-
to-source current with short circuit connection
from gate to source.
 IDSS is the max drain current for a JFET and is
defined by the conditions VGS=0V and VDS > |
Vp|.
At the pinch-off point:

Any further increase in VGS does

not produce any increase in ID.
VGS at pinch-off is denoted as Vp.

•ID is at saturation or maximum.

It is referred to as IDSS.

 The ohmic value of the channel is at

maximum.
 VGS < 0, VDS at some positive value

 VGS is the controlling voltage of the JFET.

 For n-channel devices, the controlling voltage VGS is made more and more negative
from its VGS = 0V level.
 The effect of the applied negative VGS is to establish
depletion regions similar to those obtained with VGS=0V
but a lower level of VDS  to reach the saturation
level at a lower level of VDS.
 When VGS = -Vp will be sufficiently negative to
establish saturation level that is essentially 0mA,
the device has been ‘turn off’.
 The level of the VGS that results in ID = 0 mA is
defined by VGS = Vp, with Vp being a negative voltage for n-
channel devices and a positive voltage or p-channel JFETs.
 When VGS = -Vp will be sufficiently negative to establish saturation level that is
essentially 0mA, the device has been ‘turn off’.
 The level of the VGS that results in ID = 0 mA is defined by VGS = Vp, with
Vp being a negative voltage for
n-channel devices and a positive
voltage or p-channel JFETs.
 In this region, JFET can
actually be employed as a variable
resistor whose resistance is
controlled by the applied gate to
source voltage.
 A VGS becomes more and more
negative; the slope of each curve
becomes more and more horizontal.
 Voltage-Controlled Resistor

• The region to the left of the pinch-

off point is called the ohmic region.
• The JFET can be used as a variable
resistor, where VGS controls the
drain-source resistance (rd). As VGS
becomes more negative, the
resistance (rd) increases.

ro
rd 
(1  V GS )2
VP
P-channel JFET:

p-Channel JFET acts the same as the n-

channel JFET,except the polarities and
currents are reversed.
 JFET p-channel type has p-type channel
which connecting drain (D) and source
(S).
 The main charge carrier for this type
of channel is hole.
 The depletion layer appears along the
n-type material at gate (G) and p-
channel.
 P-Channel JFET Characteristics

As VGS increases more positively:

 The depletion zone increases
 ID decreases (ID < IDSS)
 eventually ID = 0A
Also note that at high levels of
VDS the JFET reaches a
breakdown situation. ID
increases uncontrollably if
VDS> VDSmax.

Figure : p-Channel JFET characteristics with V DSS 6

mA and Vp =+6 V .
Transfer Characteristics:
• Transfer characteristic for FET is different from BJT.
• For BJT the relationship is shown below;
Control variable
I C  I B
Constant
• But for JFET, the relationship between ID and VGS is defined
by Shockley’s equation:
Control variable
2
 VGS 
I D  I DSS 1  
 VP  Constants
• We can see here, the relationship is not linear between input
and output quantities.
 Plotting the Transfer Curve:
Shockley’s Equation Methods.
• Using IDSS and Vp ( VGS(off)) values found in a specification sheet, the Transfer Curve
can be plotted using these 3 steps:
V GS 2
ID  IDSS (1 )
• Step 1: VP
• ID  IDSS
Solving for VGS = 0V: VGS  0V

V GS 2
• Step 2: ID  IDSS (1 )
VP
• Solving for VGS = Vp (VGS(off)): ID  0 A
VGS  VP

• Step 3: Solving for VGS = 0V to Vp: VGS 2

ID  IDSS(1 )
VP
Shorthand method:
VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA
Transfer Curve:

From this graph it is easy to determine the value of I D for a given value of VGS.
 FET Biasing

Introduction:
Another distinc difference between the analysis of BJT and FET transistors
is that the input controlling variable for a BJT transistor is a current level, while for the
FET a Voltage is a controlling variable.In both case, however, the controlled variable on
the output side is a current level that also defines the important voltage level of the
output circuit.
The general relationship that can be applied to the dc analysis of all amplifiers
are :

For JFETS and depletion-type MOSFETs shockley’s equation is applied to relate the
input and output quantities:
 For Enhanchement-type MOSFETs :

It is particularly important to realize that all of the equations above are for the device
only!. They do not change with each network configuration so long as the device is in
active region.
Common FET Biasing Circuit :
JFET
(i) Fixed – Bias
(ii)Self-Bias
(ii)Voltage-Divider Bias
Depletion-Type MOSFET
(i) Self-Bias
(ii)Voltage-Divider Bias
Enhancement-TypeMOSFET
(i)Feedback Configuration
(ii)Voltage-Divider Bias
FIXED-BIAS CONFIGURATION:

DC bias of a FET device needs setting of gate-

source voltage VGS to give desired drain current ID .
For a JFET drain current is limited by the saturation
current IDS. Since the FET has such a high input
impedance that no gate current flows and the dc
voltage of the gate set by a voltage divider or a fixed
battery voltage is not affected or loaded by the FET.
Fixed dc bias is obtained using a battery VGG. This
battery ensures that the gate is always negative with
respect to source and no current flows through
resistor RG and gate terminal that is IG =0.
The battery provides a voltage VGS to bias the N-
channel JFET, but no resulting current is drawn
from the battery VGG.
Resistor RG is included to allow any ac signal
applied through capacitor C to develop across RG.
While any ac signal will develop across RG, the dc
voltage drop across RG is equal to IG RG i.e. 0 volt.
IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
Since V is a fixed dc supply, the voltage VGS is
fixed in magnitude, resulting in the notation “fixed-
bias configuration”.
The resulting level of drain current I is now
controlled by Shockley’s equation.
Characteristics:
Graphical analysis would require a plot of Shockley’s equation:

When- VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA
Self-Bias Configuration:

This is the most common method for biasing a

JFET. Self-bias circuit for N-channel JFET is
shown in figure.
Since no gate current flows through the reverse-
biased gate-source, the gate current IG = 0 and,
therefore,vG = iG RG = 0
With a drain current ID the voltage at the S is
Vs= ID Rs
The gate-source voltage is then
VGs = VG - Vs = 0 – ID Rs = – ID Rs
So voltage drop across resistance Rs provides
the biasing voltage VGg and no external source is
required for biasing and this is the reason that it is
called self-biasing.
 Characteristics:
Draw the device transfer characteristic
Then, a straight line has to be defined on the same graph by identifying two points.
Point (1); The most obvious condition to apply is ID = 0 A since it results in
VGS = -IDRS =(0 A)RS = 0 V. Therefore, the first point is ID = 0A and VGS = 0V.
Point (2): For example, we choose a level of ID equal to one-half the saturation level.

I DSS
ID  then
2
The straight line is drawn usingIthe Rabove two points and the quescient point obtained
VGS   DSS S
at the intersection of the straight-line2 plot and the device characteristic curve.
The quescient values of ID and VGS can then be determined and used to find the other
quantities of interest.
Figure: Sketching the self-bias line.
Voltage-Divider Bias:

A slightly modified form of dc bias is

provided by the circuit shown in figure. The
resistors RGl and RG2 form a potential divider
across drain supply VDD. The voltage V2
across RG2 provides the necessary bias. The
additional gate resistor RGl from gate to
supply voltage facilitates in larger
adjustment of the dc bias point and permits
use of larger valued RS.
The gate is reverse biased so that IG = 0
and gate voltage
VG =V2 = (VDD/R G1 + R G2 ) *RG2
And
VGS = vG – vs = VG - ID Rs
 The circuit is so designed that ID RS is greater than VG so that VGS is negative.
The provide current bias voltage.
The operating point can be determined as
ID = (V2 – VGS)/ RS
And
VDS = VDD – ID (RD + RS)

Figure : voltage-divider Figure: Effect of RS on the

configuration
resulting Q-point