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Eee ZG512-L2
Eee ZG512-L2
BITS Pilani
K K Birla Goa Campus
Cache
High speed memory design is costly Complex , support circuitry is also costly
CPU
Cache
Controller
Cach
e
Main
Memory
Address
Example
Assume that the system has a two-level cache:
The level-1 cache has a hit rate of 90% and the level-2 cache has a
hit rate of 97%.
The level 1 cache access time is 4 ns, the level 2 cache access time is
15ns and access time of main memory is 80 ns.
What is the average memory access time?
Solution
h1 0.9
h2 - 0.1 x 0.97
tav = h1tL1 + h2tL2 + (1-h1 -h2)tmain
tav = 0.9 x 4ns + 0.097 x 15ns + (1-0.9-0.097) 80ns
5.295 ns
Memory Data
Register (MDR)
Cache
Memory Address
Register (MAR)
Cache Architecture
2H+20(1-H) < 16
Minimum Hit rate = 22 %
BITS Pilani, K K Birla Goa Campus
Page
0
Block 1
Block 2
Block 3
Block 0
Page
1
Cache
Block 1
Block 2
Block 0
Block 3
Block 1
Block 0
Page
2
Block 1
Block 2
Block 2
Block 3
Block 3
Block 0
Page
3
Block 1
Block 2
Block 3
Main
Memory
ESD @ Meetha V Shenoy
11
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
If the data is read by the processor in the following order from the
addresses
0000
0001
0100
1000
Show the contents of the cache for direct-mapped; four line cache
with each read operation. The data is read as bytes
Solution
Main Memory Address 4 bits
Cache 4 line
Tag 2- bits
Block No. 2bits
00 01
Solution
Block
00
Tag
0000
F8
0001
56
0010
3A
0011
1001
1010
AD
BC
79
1011
78
0100
67
1100
96
0101
8D
1101
70
0110
9B
1110
00
0111
78
1000
91
1111
FF
Data
01
10
11
BITS Pilani, K K Birla Goa Campus
Cold Miss
Block
00
Tag
00
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Data
F8
01
10
11
BITS Pilani, K K Birla Goa Campus
Cold Miss
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Block
00
Tag
00
Data
F8
01
00
56
10
11
BITS Pilani, K K Birla Goa Campus
Conflict Miss
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Block
00
Tag
00
Data
F8
01
00
56
10
11
BITS Pilani, K K Birla Goa Campus
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Block
00
Tag
01
Data
67
01
00
56
10
11
BITS Pilani, K K Birla Goa Campus
Conflict Miss
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Block
00
Tag
10
Data
91
01
00
56
10
11
Problem 4
If the data is read by the processor in the following order from the
addresses
1001
0001
0101
1101
Show the contents of the cache for 2 way set associative, two line
cache after every read operation.
Solution
Main Memory Address 4 bits
Block No. 1 bit
Tag 3- bits
000 1
Solution
Block
Tag
Data
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
0
1
Set 0
Set 1
BITS Pilani, K K Birla Goa Campus
Cold Miss
Block
Tag
Data
100
AD
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
0
1
Set 0
Set 1
BITS Pilani, K K Birla Goa Campus
Cold Miss
Block
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
Tag
Data
100
AD
000
56
0
1
Set 0
Set 1
BITS Pilani, K K Birla Goa Campus
Conflict Miss
Block
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
Tag
Data
100
AD
000
56
0
1
Set 0
Set 1
BITS Pilani, K K Birla Goa Campus
Conflict Miss
Block
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
Tag
Data
010
8D
000
56
0
1
Set 0
Set 1
Conflict Miss
Block
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
Tag
Data
100
8D
000
56
0
1
Set 0
Set 1
Conflict Miss
Block
0000
F8
0001
56
0010
3A
0011
79
0100
67
0101
1001
1010
AD
BC
1011
78
1100
96
8D
1101
70
0110
9B
1110
00
0111
78
1111
FF
1000
91
Tag
Data
Tag
Data
010
8D
110
70
0
1
Set 0
Set 1
BITS Pilani, K K Birla Goa Campus
Replacement Policy
Least recently used (LRU)
Most recently used (MRU)
Random replacement
Increases variability of memory
access time Not suitable for safety
critical Applications
Unified Cache
Instruction Cache / Data cache
Problem 5
You are assigned to analyze a segment of code for an
Embedded System so as to provide a solution to
improve the performance. The embedded system uses
an hierarchical memory organization with single level of
cache. The memory initializations are shown followed by
the code.
int i=0 ;
int u[15] ; u is an int array of 15 members u[0] to u[14]
int v[15] ; v is an int array of 15 members u[0] to u[14]
int w[3];
int x[4] ;
int y[5] ;
int z=0 ;
for (i=0 ;i<15 ;i++)
{
z=z+ u[i]*v[i]; Multiply and Accumulate
}
int refers to 32 bit data. The variables i, z are stored in registers where
as the int arrays u, v, w, x, y is mapped to RAM(Main memory).
Main Memory:
Cache Memory:
Page 0
Page 1
Cache
U[0)
V(1)
U(1)
V(2)
V[1)
U[0)
V[1)
V(2)
U(1)
V(2)
U(2)
V(3)
V(3)
U(2)
V(3)
U(3)
V(4)
V(4)
U(3)
V(4)
U(4)
V(5)
U[4)
V[5)
U(5)
V(6)
U(5)
V(6)
U(6)
V(7)
U(6)
V(7)
U(7)
V(8)
U(8)
V(9)
U(7)
V(8)
U(8)
V(9)
V(9)
U(9)
V(10)
V(10)
U(9)
V(10)
U(10)
V(11)
U(10)
V(11)
V(11)
U(11)
V(12)
U(11)
V(12)
V(12)
U(12)
V(13)
U[12)
U(13)
V(14)
U(13)
U(14)
W(0)
U(14)
V(0)
W(1)
V(0)
u[0]miss
u[1]-hit
u[2]miss
u[3]miss
u[4]miss
u[5]-hit
u[6]miss
u[7]miss
u[8]miss
u[9]-hit
u[10]miss
u[11]miss
u[12]-hit
v[0]-miss
v[1]-miss
v[2]-miss
[3]-miss
v[4]-hit
v[5]-miss
v[6]-miss
v[7]-miss
v[8]-hit
v[9]-miss
v[10]miss
v[11]miss
v[12]-hit
v[13]miss
v[14]miss
Write through
Write back
Dirty bit
Discussion focus
Advantage of Introducing Cache Memory
Improving Cache hit via cache mapping schemes
Improving Cache hit via optimal programming
39
BITS Pilani, K K Birla Goa Campus