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JTAG Scanning Principles
JTAG Scanning Principles
Module Contents
* Scan Fundamentals
Full and partial scan techniques
Level sensitive and edge triggered methods
* JTAG and the Test Access Port (TAP)
JTAG Interface Signals
Test Access Port Controller
Test Access Port Instructions
Scan Basics
* Flip-flop elements within a circuit can be connected serially to
form a shift register structure.
* Access to the scan chain data via 2 pins, Test Data In (TDI) and
Test Data Out (TDO).
* Data can be applied serially on TDI to set up the system state,
while state data can be read serially on TDO.
Serial Scan
*
*
*
*
G1
1
1
To next
cell
1D
C1
1D
C1
G1
1
1
From logic
or pin
Clock
Scan and JTAG Principles
Update
To logic
or pin
Mode
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Scan Nomenclature
* Full Scan
Connection of all flip-flop elements into a single serial shift
register.
* Partial Scan
Connection of a subset of all flip-flop elements to form a serial
shift register.
There can be more than one partial scan chain.
* Boundary Scan
All I/Os are isolated from the core logic by a serial shift register.
This shift register can be used to apply system-level stimuli to the
core serially.
TAP
Control
TAP
Control
TAP
TDI
TCK
TMS
TRST
TDO
Boundary-Scan
Cell
Test Registers
and Decoder
TAP
Controller
TAP
Control
Package Pin
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TAP Architecture
Test Data Registers
Device ID Register
Bypass register
Instruction Decode
TDO
TDI
TMS
TCK
nTRST
Instruction Reg.
TAP
Controller
nTDOEN
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Test-Logic
Reset
TMS=0
Run-Test/Idle
TMS=0
TMS=1
TMS=1
Select-DR-Scan
TMS=1
Select-IR-Scan
TMS=0
TMS=0
TMS=1
Capture-DR
TMS=0
Shift-IR
TMS=0
Exit1-IR
TMS=0
TMS=0
TMS=0
Pause-DR
TMS=1
TMS=1
TMS=0
Pause-IR
TMS=0
Exit2-DR
TMS=1
Exit2-IR
TMS=1
TMS=1
Update-DR
TMS=1
TMS=0
TMS=1
TMS=1
Exit1-DR
TMS=0
Capture-IR
TMS=0
TMS=0
Shift-DR
TMS=1
Update-IR
TMS=0
TMS=1
TMS=0
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Controller States I
* TEST-LOGIC-RESET
Test logic disabled; allows for normal chip operation.
* RUN-TEST-IDLE
Controller state between scan operations.
* SELECT-DR/IR-SCAN
Temporary controller states in which all test data registers selected
by the current instruction retain their current state.
Initiates register scan sequence.
* CAPTURE-DR
The selected test data register captures its data inputs on the rising
edge of TCK.
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Controller States II
* CAPTURE-IR
The instruction register loads a fixed bit pattern on rising TCK.
* SHIFT-DR/IR
In these states the test data register (DR) or the instruction register
(IR), shifts its data by one stage on each rising edge of TCK.
* EXIT1-DR/IR
These are temporary controller states. If TMS = 1, then on the next
rising TCK, the state machine will enter the Update-DR/IR states.
* UPDATE-DR
Some test data registers have latched parallel outputs.
These outputs are latched on falling TCK
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TAP Instructions I
* SCAN_N (0010)
Connects the Scan Path Select Register between TDI and TDO.
Selects scan chain for subsequent test operations.
* EXTEST (0000)
Allows for testing of external logic.
During SHIFT-DR scanned-in data is applied immediately to the
system.
* INTEST (1100)
Allows for testing of internal logic.
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TAP Instructions II
* IDCODE (1110)
Connects device identification register between TDI and TDO.
* BYPASS (1111)
Connects a single stage shift register between TDI and TDO.
Allows testing of individual devices to take place.
* CLAMP (0101)
Connects a single stage shift register between TDI and TDO.
Output signals are defined by values previously loaded into the
currently selected scan chain.
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Summary
* Serial test methods offer a route towards an automated method of
providing test coverage.
* IEEE 1149 extends this serial test architecture to cover system
level testing.
* ARM implements key components of the 1149 standard within its
debug-aware cores, but requires external support to completely
adhere to the standard.
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