Inverter fabrication

Basic CMOS Process

Flow

Silicon Epi Layer P

~2 microns

Starting Point: Pure silicon

wafer (heavily-doped) with a
lightly-doped epitaxial (epi)
layer.

~725 microns

An epi layer is used to provide a

cleaner layer for device
formation and to prevent latchup of CMOS transistors.
Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Grow Pad Oxide: A very thin (~200A) layer

of silicon dioxide (SiO2) is grown on the surface
by reacting silicon and oxygen at high
temperatures. This will serve as a stress relief
layer between the silicon and the subsequent
nitride layer.
Pad Oxide

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Deposit Silicon Nitride: A layer (~2500A) of

silicon nitride (Si3N4) is deposited using
Chemical Vapor Deposition. This will serve as a
polish stop layer during trench formation.

Silicon Nitride

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Pattern Photoresist for Definition of

Trenches: One of the most critical patterning
steps in the process. 0.5 - 1.0 microns of resist is
spun, exposed, and developed.
Photoresist
Silicon Nitride

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Etch Nitride and Pad Oxide: A reactive ion

etch (RIE) utilizing fluorine chemistry is used.

Photoresist
Silicon Nitride

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Etch Trenches in Silicon: A reactive ion

etch (RIE) utilizing fluorine chemistry is used.
Defines transistor active areas.
Isolation Trenches

Photoresist
Silicon Nitride

Transistor Active Areas

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Remove Photoresist: An oxygen plasma is

used to burn off the resist layer.
Isolation Trenches

Silicon Nitride

Transistor Active Areas

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Fill Trenches with Oxide: A CVD oxide

layer is deposited to conformally fill the trenches.
The oxide will prevent cross-talk between the
transistors in the circuit.
No current can flow
through here!
Silicon Dioxide
Silicon Nitride
Future PMOS Transistor

Future NMOS Transistor

Silicon Epi Layer P

Silicon Substrate P+

Basic CMOS Process Flow - Shallow Trench Formation

Polish Trench Oxide: The surface oxide is

removed using a Chemical Mechanical Polish
(CMP). The CMP process is designed to stop on
silicon nitride.
No current can flow
through here!

Silicon Nitride
Future PMOS Transistor

Future NMOS Transistor

Silicon Epi Layer P

Silicon Substrate P+

10

Basic CMOS Process Flow - Shallow Trench Formation

Remove Silicon Nitride: A wet etch in hot

phosphoric acid (H3PO4) is used, completing
formation of Shallow Trench Isolation (STI).

Future PMOS Transistor

Future NMOS Transistor

Silicon Epi Layer P

Silicon Substrate P+

11

Basic CMOS Process Flow - Well Formation

Pattern Photoresist for N-Well

Formation: A non-critical masking layer,
utilizing thicker resist to block the implant.
Photoresist

Future PMOS Transistor

Future NMOS Transistor

Silicon Epi Layer P

Silicon Substrate P+

12

Basic CMOS Process Flow - Well Formation

Implant N-Well: A deep (high-energy)

implant of phosphorous ions creates a localized
N-type region for the PMOS transistor.
Phosphorous (-) Ions

Photoresist

Future NMOS Transistor

N Well

Silicon Epi Layer P

Silicon Substrate P+

13

Basic CMOS Process Flow - Well Formation

Strip N-Well Photoresist:

Future NMOS Transistor

N Well

Silicon Epi Layer P

Silicon Substrate P+

14

Basic CMOS Process Flow - Well Formation

Pattern Photoresist for P-Well

Formation: A non-critical masking layer,
utilizing thicker resist to block the implant.

Photoresist

Future NMOS Transistor

N Well

Silicon Epi Layer P

Silicon Substrate P+

15

Basic CMOS Process Flow - Well Formation

Implant P-Well: A deep (high-energy)

implant of boron ions creates a localized P-type
region for the NMOS transistor.
Boron (+) Ions

Photoresist

N Well

P Well

Silicon Epi Layer P

Silicon Substrate P+

16

Basic CMOS Process Flow - Well Formation

Strip P-Well Photoresist:

N Well

P Well

Silicon Epi Layer P

Silicon Substrate P+

17

Basic CMOS Process Flow - Well Formation

Anneal Well Implants: This step repairs

damage to the silicon surface caused by the
implants and electrically activates the dopants. It
also drives the dopants somewhat deeper, but
Rapid Thermal Processing is used to minimize
dopant spreading.

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

18

Basic CMOS Process Flow - Gate Formation

Grow Sacrificial Oxide: A thin (~250A)

oxide layer is grown to capture defects in the
silicon surface.
Sacrificial Oxide

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

19

Basic CMOS Process Flow - Gate Formation

Remove Sacrificial Oxide: Sac ox is

immediately removed in a wet HF solution,
leaving behind a clean silicon surface.

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

20

Basic CMOS Process Flow - Gate Formation

Grow Gate Oxide: This is the most critical

step in the process! A very thin (20-100A) oxide
layer is grown that will serve as the gate dielectric
for both transistors. It must be extremely clean,
and grown to a very precise thickness (+/- 1A).

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

21

Basic CMOS Process Flow - Gate Formation

Deposit Polysilicon: Polycrystalline silicon is

deposited using Chemical Vapor Deposition to a
thickness of 1500-3000 angstroms.

Polysilicon

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

22

Basic CMOS Process Flow - Gate Formation

Pattern Photoresist to Define Gate Electrodes:

This is the most critical patterning step in the
process! Precise sizing of the poly gate length is a firstorder determinant of transistor switching speed. The
highest-technology patterning systems are used (i.e.
DUV) along with thinner-than-normal photoresist due to
the critical nature of the layer.
Channel Length

Photoresist
Polysilicon

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

23

Basic CMOS Process Flow - Gate Formation

Etch Polysilicon and Strip Resist: Reactive Ion

Etching using fluorine chemistry is used. The completes
the formation of the gate stack.
Poly Gate Electrode
Gate Oxide

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

24

Basic CMOS Process Flow - Gate Formation

Oxidize Polysilicon: A thin layer of oxide is grown on top
of the polysilicon to act as a buffer between the poly and the
subsequent silicon nitride layer.
Poly Re-oxidation
Poly Gate Electrode
Gate Oxide

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

25

Basic CMOS Process Flow - Source/Drain Formation

Pattern Photoresist for NMOS Transistor Tip

Implant:

Photoresist

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

26

Basic CMOS Process Flow - Source/Drain Formation

NMOS Transistor Tip Implant: A very shallow (low

energy) and low dose implant of arsenic ions begins the
formation of the NMOS transistor source and drain. The tip
will serve to reduce hot electron effects near the gate region.
Arsenic (-) Ions

Photoresist
N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

27

Basic CMOS Process Flow - Source/Drain Formation

Strip Photoresist:

N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

28

Basic CMOS Process Flow - Source/Drain Formation

Pattern Photoresist for PMOS Transistor Tip

Implant:

Photoresist
N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

29

Basic CMOS Process Flow - Source/Drain Formation

PMOS Transistor Tip Implant: A very shallow (low

energy) and low dose implant of BF2 ions begins the formation
of the PMOS transistor source and drain. The tip will serve
to reduce hot electron effects near the gate region.
BF2 (+) Ions

Photoresist
P Tip

N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

30

Basic CMOS Process Flow - Source/Drain Formation

Strip Photoresist:

P Tip

N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

31

Basic CMOS Process Flow - Source/Drain Formation

Deposit Silicon Nitride Layer: Using

Chemical Vapor Deposition, thickness 1200Thinner Here
1800A.
Thicker Here

P Tip

N Tip

N Well

Silicon Nitride

P Well
Silicon Epi Layer P
Silicon Substrate P+

32

Basic CMOS Process Flow - Source/Drain Formation

Etch Nitride to Form Spacer Sidewalls: Using a
carefully controlled RIE etch, the thin nitride is removed from
the horizontal surfaces, but the sidewalls remain. These
sidewalls will precisely position the implants that form the
Spacer Sidewall
transistor sources and drains.

P Tip

N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

33

Basic CMOS Process Flow - Source/Drain Formation

Pattern Photoresist for NMOS Transistor

Source/Drain Implant:

Photoresist
P Tip

N Tip

N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+

34

Basic CMOS Process Flow - Source/Drain Formation

NMOS Transistor Source/Drain Implant: A shallow
and high-dose implant of arsenic ions completes the formation
of the heavily-doped NMOS transistor source and drain. The
spacer shadows the implant near the gate region.
Arsenic (-) Ions

Photoresist
P Tip

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

35

Basic CMOS Process Flow - Source/Drain Formation

Strip Photoresist:

P Tip

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

36

Basic CMOS Process Flow - Source/Drain Formation

Pattern Photoresist for PMOS Transistor

Source/Drain Implant:

Photoresist
P Tip

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

37

Basic CMOS Process Flow - Source/Drain Formation

PMOS Transistor Source/Drain Implant: A shallow
and high-dose implant of BF2 ions completes the formation of
the heavily-doped PMOS transistor source and drain. The
spacer shadows the implant near the gate region.
BF2 (+) Ions

Photoresist
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

38

Basic CMOS Process Flow - Source/Drain Formation

Strip Photoresist and Anneal Implants: Use

Rapid Thermal Annealing to virtually eliminate
dopant migration in the shallow source and drains.
The electronic devices are now completely formed.
All that remains is to connect them together.
Lightly Doped Tips

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

39

Basic CMOS Process Flow - Salicide Formation

Strip Surface Oxides: A quick dip in HF to expose

bare silicon in the source, gate, and drain areas.

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

40

Basic CMOS Process Flow - Salicide Formation

Deposit Titanium: Use a sputterer to deposit a

thin (200-400A) layer of titanium across the entire
wafer surface.

P Source

P Drain

N Source

N Well

Titanium
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

41

Basic CMOS Process Flow - Salicide Formation

Titanium Silicide Formation: Rapid Thermal

Processing in nitrogen at 800 Degrees C causes the titanium to
react with silicon, forming titanium silicide, where the two are
in contact. In other areas, the titanium is unchanged. This
process perfectly aligns the silicide to the exposed silicon, and
is called Self-Aligned Silicide, or Salicide.
Unreacted Titanium
Titanium Silicide

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

42

Basic CMOS Process Flow - Salicide Formation

Titanium Etch: The unreacted titanium is

removed using a wet etch in NH4OH + H2O2. The
titanium silicide remains. TiSi2 provides an ohmic
contact between silicon and metal.
Titanium Silicide

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

43

Basic CMOS Process Flow - 1st Interconnect Layer

Deposit BPSG: Silicon dioxide doped with small amounts

of boron and phosphorous to enable film reflow and to getter
contaminants. Deposited using Chemical Vapor Deposition.
Approximate thickness is 1 micron. This layer will
electrically insulate the devices from the 1st metal layer.

BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

44

Basic CMOS Process Flow - 1st Interconnect Layer

Polish BPSG: Use Chemical Mechanical Polishing to

achieve a flat surface on the BPSG layer. If not removed, the
bumps on the surface from the underlying topography would
cause a problem for the subsequent photolithography steps and
degrade metal step coverage.

BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

45

Basic CMOS Process Flow - 1st Interconnect Layer

Pattern Photoresist to Define Contacts: Contacts are

openings in the BPSG layer enabling electrical access to the
devices below. This is a critical photolithography step.

Photoresist
BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

46

Basic CMOS Process Flow - 1st Interconnect Layer

Contact Etch: A carefully designed RIE etch using

fluorine chemistry to achieve vertical sidewalls.

Photoresist
BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

47

Basic CMOS Process Flow - 1st Interconnect Layer

Strip Photoresist:

BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

48

Basic CMOS Process Flow - 1st Interconnect Layer

Titanium Nitride Deposition: A sputterer is used to

deposit TiN to a thickness of about 200A. This layer will
help the subsequent tungsten layer to adhere to the oxide.

Titanium Nitride

BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

49

Basic CMOS Process Flow - 1st Interconnect Layer

Tungsten Deposition: Tungsten is chosen because it

deposits conformally (via CVD) and can fill the contact holes.
The thickness must be at least half of the diameter of the
contact.
Titanium Nitride
Tungsten
BPSG
P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

50

Basic CMOS Process Flow - 1st Interconnect Layer

Polish Tungsten: CMP is used to remove the surface

tungsten. The remaining tungsten forms plugs. The surface
titanium nitride is also removed.

BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

51

Basic CMOS Process Flow - 1st Interconnect Layer

Deposit Metal1 Layer: Each interconnect layer is actually
a sandwich of different layers. A sample is shown below. The
films are deposited by sputtering.
TiN (500A) - antireflective coating
AlCu (5000A) - main conductor
TiN (500A) - diffusion barrier
Ti (200A) - electromigration shunt
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

52

Basic CMOS Process Flow - 1st Interconnect Layer

Pattern Photoresist for Metal1 Interconnects:

Photoresist
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

53

Basic CMOS Process Flow - 1st Interconnect Layer

Etch Metal1: An RIE etch utilizing chlorine chemistry.

Multiple etch steps are required due to the multiple different
metal layers.

Photoresist
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

54

Basic CMOS Process Flow - 1st Interconnect Layer

Strip Photoresist: First interconnect layer is completed.

Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

55

Basic CMOS Process Flow - 2nd through Nth (as many as

8) Interconnect Layer
Deposit IMD1: Undoped silicon dioxide is deposited using
successive CVD depositions and etches to achieve filling
between metal lines. Approximate thickness is 1 micron. This
layer will electrically insulate the metal layers from one
another.
IMD1
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+
56

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer
Polish IMD1: Use Chemical Mechanical Polishing to
achieve a flat surface on the IMD layer. If not removed, the
bumps on the surface from the underlying topography would
cause a problem for the subsequent photolithography steps and
degrade metal step coverage.
IMD1
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+
57

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Pattern Photoresist to Define Vias: Vias are contact

openings in the IMD layers enabling electrical access between
metal layers.
Photoresist
IMD1
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

58

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Via Etch: A carefully designed RIE etch using fluorine

chemistry to achieve vertical sidewalls.
Photoresist
IMD1
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

59

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Strip Photoresist:

IMD1
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

60

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Deposit Titanium Nitride and Tungsten: Same as for

the first interconnect layer.
Tungsten
IMD1
Metal1
BPSG
P+ Source

P+ Drain

N+ Source

N Well

W Contact Plug
N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

61

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Polish Tungsten:

IMD1

W Via Plug

BPSG

W Contact Plug

Metal1

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

62

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Deposit Metal2: Subsequent metal stacks will be similar to

Metal1 but tend to increase in thickness and width as their
runs are longer and they carry more current.
Metal2
IMD1

W Via Plug

BPSG

W Contact Plug

Metal1

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

63

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Pattern Photoresist for Metal2 Interconnects:

Adjacent metal layers are patterned perpendicular to each other
to minimize inductive coupling between layers (not shown in
cross-sectional diagram).
Photoresist

Metal2
IMD1

W Via Plug

BPSG

W Contact Plug

Metal1

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+
64

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Etch Metal2: An RIE etch utilizing chlorine chemistry.

Multiple etch steps are required due to the multiple different
metal layers.
Photoresist
Metal2
IMD1

W Via Plug

BPSG

W Contact Plug

Metal1

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

65

Basic CMOS Process Flow - 2nd through Nth

interconnect Layer

Strip Photoresist: 2nd interconnect layer is completed.

Metal2
IMD1

W Via Plug

BPSG

W Contact Plug

Metal1

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+

66

Basic CMOS Process Flow - Passivation

Deposit Passivation Layer: There are many types of

passivation (silicon nitride, silicon oxynitride, polyimide, and
others). Its purpose is to protect the completed circuit from
scratches, contamination, and moisture.
Passivation
Metal2
IMD1

W Via Plug

BPSG

W Contact Plug

Metal1

P+ Source

P+ Drain

N+ Source

N Well

N+ Drain

P Well
Silicon Epi Layer P
Silicon Substrate P+
67

Basic CMOS Process Flow - Passivation

Pattern Passivation Layer: Polyimide passivation is

photo-definable. Other passivation layers require a patterned
photoresist layer followed by an etch step. Bond pad openings
allow electrical access to the chip.
Bond Pad
Passivation
Metal2
IMD1

W Via Plug

BPSG

W Contact Plug

Metal1
Silicide

Poly Gate

P+ Source

Spacer
P+ Drain

N+ Source

N+ Drain

Gate Oxide
N Well

P Well
Silicon Epi Layer P
Silicon Substrate P+
68

Basic CMOS Process Flow

Now Lets Review!!

69