PIPELINING

Basic Concepts

Use the Idea of Pipelining in a

Computer
Fetch + Execution
I1

I2

T ime

I3

Clockcycle
F

I2
Interstagebuffer
B1
Instruction
fetch
unit

I3
Execution
unit

(b)Hardwareorganization

F1

E1

Instruction
I1

(a)Sequentialexecution

F2

E2
F3

(c)Pipelinedexecution

E3

Time

4 stage Pipelining in a Computer

Time
Clockcycle

F1

D1

E1

W1

F2

D2

E2

W2

F3

D3

E3

W3

F4

D4

E4

Instruction

Fetch + Decode
+ Execution + Write

I1
I2
I3
I4

W4

(a)Instructionexecutiondividedintofoursteps
Interstagebuffers

D:Decode
instruction
andfetch
operands

F:Fetch
instruction
B1

E:Execute
operation
B2

(b)Hardwareorganization

Figure8.2. A4stagepipeline.

W:Write
results
B3

Role of Cache Memory

Each pipeline stage is expected to complete
in one clock cycle.
The clock period should be long enough to let
the slowest pipeline stage to complete.
Faster stages can only wait for the slowest
one to complete.
Since main memory is very slow compared to
the execution, if each instruction needs to be
fetched from main memory, pipeline is almost
useless.
Fortunately, we have cache.

Pipeline Performance
Pipelined processor completes the
processing of one instruction in each clock
cycle.
i.e. the rate of instruction processing is 4
times that of sequential operation.
But a pipe line may be interrupted due to
variety of reasons, and its stage cannot
complete the operation within one clock
cycle.
Eg. It is assumed that every operation is
completed in a single clock cycle. But
some operations such as divide may take
more than one clock cycle to complete.

Pipeline Performance
Time
Clockcycle

F1

D1

E1

W1

F2

D2

Instruction
I1
I2
I3
I4

I5

F3

E2

W2

D3

E3

W3

F4

D4

E4

W4

F5

D5

E5

Figure8.3. Effectofanexecutionoperationtakingmorethanoneclockcycle.

Pipeline Performance
The previous pipeline is said to have been
stalled for two clock cycles.
Any condition that causes a pipeline to stall is
called a hazard.

Three types of hazards:

Data Hazard
Instruction Hazard or Control Hazard
Structural Hazard

HAZARD TYPES

Data hazard
Pipelined is stalled due to the nonavailability of source/destination Operands
(date).
Instruction (control) hazard
Pipeline is stalled because of the delay
in the availability of an instruction or
unavailability of an instruction . [May be
due to cache miss].
Structural hazard
The situation when two instructions
require the use of a given hardware

Instruction (control)
hazard
Time

Clockcycle

F1

D1

E1

W1

D2

E2

W2

F3

D3

E3

W3

Instruction
I1
I2

F2

I3

(a)Instructionexecutionstepsinsuccessiveclockcycles
Time
Clockcycle

F1

F2

F2

F2

F2

F3

D1

idle

idle

idle

D2

D3

E1

idle

idle

idle

E2

E3

W1

idle

idle

idle

W2

Stage
F:Fetch
D:Decode
E:Execute
W:Write

W3

(b)Functionperformedbyeachprocessorstageinsuccessiveclockcycles

Figure8.4.

PipelinestallcausedbyacachemissinF2.

Idle periods
stalls
(bubbles)

Structural hazard
Load X(R1),
R2
Time
Clockcycle

F1

D1

E1

W1

F2

D2
F3

E2

M2

W2

D3

E3

W3

F4

D4

E4

Instruction
I1
I2 (Load)
I3
I4

I5

F5

Figure8.5.

D5

EffectofaLoadinstructiononpipelinetiming.

Pipeline Performance
Again, pipelining does not result in individual
instructions being executed faster; rather, it is
the throughput that increases.
Throughput is measured by the rate at which
instruction execution is completed.
Pipeline stall causes degradation in pipeline
performance.
We need to identify all hazards that may
cause the pipeline to stall and to find ways to
minimize their impact.