Execution of Branch

Instructions
A branch instruction replaces the
contents of PC with the branch target
address, which is usually obtained by
adding an offset X given in the
branch instruction.
The offset X is usually the difference
between the branch target address
and the address immediately
following the branch instruction.
Conditional branch

Execution of Branch
Instructions
StepAction
1

PCout , MAR in , Read,Select4,Add, Zin

Zout, PCin , Yin, WMF C

MDRout , IR in

4
5

Offset-field-of-IR
out, Add, Zin
Zout, PCin , End

Figure 7.7. Control sequence for an unconditional branch instruction.

Multiple-Bus Organization
BusA

BusB

BusC
Incrementer

PC

Register
file

MUX

Constant4

A
ALU R
B

Instruction
decoder

IR

MDR

MAR

Memorybus
datalines

Address
lines

Figure7.8. Threebusorganizationofthedatapath.

Multiple-Bus Organization

Add R4, R5, R6

StepAction
1

PCout, R=B, MAR in , Read, IncPC

WMFC

MDRoutB, R=B, IR in

R4outA, R5outB, SelectA,Add, R6in, End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.

Quiz
Internalprocessor
bus
Controlsignals

What is the
control sequence
for execution of
the instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)

PC
Instruction

Address
lines

decoderand
MAR

controllogic

Memory
bus
MDR

Data
lines

IR

Y
R0

Constant4
Select

MUX
Add

ALU
control
lines

Sub

R n 1

ALU
Carryin

XOR

TEMP
Z

Figure7.1.Singlebusorganizationofthedatapathinsideaprocessor.

Hardwired Control

Overview
To execute instructions, the
processor must have some means of
generating the control signals
needed in the proper sequence.
Two categories: hardwired control
and microprogrammed control
Hardwired system can operate at
high speed; but with little flexibility.

Control Unit Organization

Clock

CLK

Controlstep
counter

External
inputs
IR

Decoder/
encoder
Condition
codes

Controlsignals

Figure7.10.Controlunitorganization.

Detailed Block Description

Clock

CLK

Controlstep
counter

Reset

Stepdecoder
T 1 T2

Tn

INS 1

External
inputs

INS 2
IR

Instruction
decoder

Encoder
Condition
codes

INSm
Run

End
Controlsignals

Figure7.11.

Separationofthedecodingandencodingfunctions.

Generating Zin
Zin = T1 + T6 ADD + T4 BR +
Branch
T4

Add
T6

T1

Figure7.12.GenerationoftheZincontrolsignalfortheprocessorinFigure7.1.

Generating End
End = T7 ADD + T5 BR + (T5 N + T4 N) BRN +
Branch<0

Add
T7

Branch

T5

T4

End

Figure7.13. GenerationoftheEndcontrolsignal.

T5

A Complete Processor
Instruction
unit

Integer
unit

Instruction
cache

Floatingpoint
unit

Data
cache

Businterface

Processor

Systembus
Main
memory

Figure7.14.

Input/
Output

Blockdiagramofacompleteprocessor.