Analog to Digital

Converters
Representing
a
continuously
varying physical quantity by a
sequence of discrete numerical
values.

03 07 10 14 09 02 00 04

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Conversion Methods
Ramp ADC
Successive Approximation
Flash Comparison

PNJ 10/28/2004

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The Comparator
Most A-D converters use a comparator
as part of the conversion process
A comparator compares 2 signals A and
B
if A > B the comparator output is in one
logic state (0, say)
if B > A then it is in the opposite state (1,
say)
analogue
comparator input
can

A
be built using an op
amp with no
feedback
reference
+
-

voltage

Digital-Ramp ADC
Conversion from analog to digital
form inherently involves comparator
action where the value of the analog
voltage at some point in time is
compared with some standard.
A common way to do that is to apply
the analog voltage to one terminal of
a comparator and trigger a binary
counter which drives a DAC.

Ramp ADC

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Digital-Ramp ADC
The output of the DAC is applied to
the other terminal of the comparator.
Since the output of the DAC is
increasing with the counter, it will
trigger the comparator at some point
when its voltage exceeds the analog
input.
The transition of the comparator stops
the binary counter, which at that point
holds the digital value corresponding
to the analog voltage.

Successive Approximation

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Successive approximation
ADC
Much faster than
the digital ramp
ADC because it
uses digital logic
to converge on the
value closest to
the input voltage.
A comparator and
a DAC are used in
the process.

Successive-Approximation A/D

analog
input

D/A Converter

Vref
Digital
Output
Data

comparator

STRT

Successive
Approximation
Register

clock

At initialization, all bits from the SAR are set to zero, and
conversion begins by taking STRT line low.

Successive-Approximation A/D

analog
input

D/A Converter

Vref
Digital
Output
Data

comparator

STRT

Successive
Approximation
Register

clock

First the logic in the SAR sets the MSB bit equal to 1
(+5 V). Remember that a 1 in bit 7 will be half of full
scale.

Successive-Approximation A/D

analog
input

D/A Converter

Vref
Digital
Output
Data

comparator

STRT

Successive
Approximation
Register

clock

The output of the SAR feeds the D/A converter producing an

output compared to the analog input voltage. If the D/A
output is < Vin then the MSB is left at 1 and the next bit is
then tested.

Successive-Approximation A/D

analog
input

D/A Converter

Vref
Digital
Output
Data

comparator

STRT

Successive
Approximation
Register

clock

If the D/A output is > Vin then the MSB is set to 0 and the
next bit is set equal to 1.

Successive bits are set and tested by comparing the DAC output to
the input Vin in an 8 step process (for an 8-bit converter) that results
in a valid 8-bit binary output that represents the input voltage.

analog input voltage

FS

D/A output for 8-bit

conversion with output
code 1011 0111

FS

FS

CLOCK PERIOD 1

Successive approximation search tree

for a 4-bit A/D
1111
1110

D/A output
compared with Vin
to see if larger or
smaller

1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001

Note that the successive approximation process takes a

fixed time - 8 clock cycles for the 8-bit example.

For greater accuracy, one must use a higher bit converter,

i.e. 10-bit, 12-bit, etc. However, the depth of the search and
the time required increases with the bit count.

Flash Comparison

If N is the number of bits in the

output word.
Then 2N comparators will be
required.

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Flash ADC
It is the fastest type of ADC
available, but requires a
comparator for each value of
output.
(63 for 6-bit, 255 for 8-bit, etc.)
Such ADCs are available in IC form
up to 8-bit and 10-bit flash ADCs
(1023 comparators) are planned.
The encoder logic executes a truth
table to convert the ladder of inputs
to the binary number output.
Illustrated is a 3-bit flash ADC with resolution 1 volt

Flash ADC
The resistor net and comparators
provide an input to the combinational
logic circuit, so the conversion time is
just the propagation delay through
the network - it is not limited by the
clock rate or some convergence
sequence.

Resolution
Misalkan bilangan biner dengan n bit
digunakan untuk mewakili nilai
analog mulai dari 0 ke A
There are 2n possible numbers
Resolution = A / 2n
FS = (2n-1) step size

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Resolution Example
Temperature range of 0 K to 300 K to
be linearly converted to a voltage
signal of 0 to 2.5 V, then digitized
with an 8-bit A/D converter
2.5 / 28 = 0.0098 V, or about 10 mV
per step
300 K / 28 = 1.2 K per step
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Resolution Example
Temperature range of 0 K to 300 K to
be linearly converted to a voltage
signal of 0 to 2.5 V, then digitized
with a 10-bit A/D converter
2.5 / 210 = 0.00244V, or about 2.4
mV per step
300 K / 210 = 0.29 K per step
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Quantization Noise
Setiap konversi memiliki ketidakpastian
rata-rata setengah ukuran langkah (A /
2N)

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Conversion Time
Waktu yang dibutuhkan untuk
memperoleh sampel dari sinyal analog dan
menentukan representasi numerik.

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