Layout Process

and
Design Rules

Intro
CMOS fabrication can be
accomplished using either of the
three technologies:
N-well/P-well technologies
Twin well technology
Silicon On Insulator (SOI)

nMOS Fabrication process

Thin wafer cut from a single crystal of
silicon
75 to 150mm dia
0.4mm thickness dopped with
impurities like boron
Substrate
P + substrate

Step 2: Layer of SiO2 is grown over the

substrate

Thick oxide (1m)

P + substrate

Step 3: layer of photo resist to get even

thickness
Photo Resist

P + substrate

Step 4: exposing the photo resist layer with

a mask to the UV light, where channel of
transistor is going to place
UV Light
Mask

P + substrate

Makes harden
expect the place
where diffusion is
going to be.

Window is created
Step 5: Etched away together with underlying silicon.

P + substrate

Step 6: remaining photo resist also

removed.
Again lay the SiO2 (0.1m) over the wafer
Polysilicon is deposited to form the gate
(chemical vapor Deposition)
P + substrate

Step 7: again photo resist and masking

allows the Polysilicon to be patterned
n type diffusion are diffused to form the
source and drain
Diffusion is achieved by heating the
wafer to the high temperature and
passing through the gas containing the
desired n type impurity
P + substrate

Step 8: thick oxide is grown over the wafer

again and then masked with photo resist to
exposed selected areas of Polysilicon gate,
source and the drain. ( for contact cuts)

Step 9: whole chip is then metal deposited over

its surface.

Layout design rules

Design rules are a set of geometrical
specifications that dictate the design of the
layout masks
A design rule set provides numerical values
o For minimum dimensions
o For minimum line spacings

Design rules must be followed to insure

functional structures on the fabricated chip
Design rules change with technological
advances (www.mosis.org)

Why we use design rules?

oInterface between designer and process
engineer
oGuidelines for constructing process masks
oManufacturing processes have inherent
limitations in accuracy.
oDesign rules specify geometry of masks which
will provide reasonable yields.
oDesign rules are determined by experience.

Manufacturing problems
Photoresist shrinkage, tearing.
Variations in material deposition.
Variations in temperature.
Variations in oxide thickness.
Impurities.
Variations between lots.
Variations across a wafer.

Transistor problems
Variations in threshold voltage:
ooxide thickness;
oion implantation;
opoly variations.

Changes in source/drain diffusion overlap.

Variations in substrate.

Wiring problems
Diffusion: changes in doping -> variations

in resistance, capacitance.
Poly, metal: variations in height, width ->

variations in resistance, capacitance.

Shorts and opens:

Oxide problems
Variations in height.
Lack of planarity -> step coverage.
metal 2
metal 2

metal 1

Via problems
Via may not be cut all the way through.
Undersize via has too much resistance.
Via may be too large and create short.

Design Rules
Minimum length or width of a feature on a layer is 2

Why?
To allow for shape contraction
Minimum separation of features on a layer is 2

Why?
To ensure adequate continuity of the

intervening materials.

Design Rules
Typical rules:
oMinumum size
oMinimum spacing
oAlignment / overlap
oComposition
oNegative features

MOSIS SCMOS design rules

Designed to scale across a wide range of

technologies.
Designed to support multiple vendors.
Designed for educational use.
Ergo, fairly conservative.

http://www.mosis.com/design/rules/

Lambda design rules

is the size of a minimum feature.
Specifying particularizes the scalable

rules.

Parasitics are generally not specified in

units

Types of Design Rules

Scalable Design Rules (e.g. SCMOS)
o Based on scalable coarse grid -(lambda)

o Idea: reducevalue for each new process, but keep rules

the same

Key advantage: portable layout

Key disadvantage: not everything scales the same
o Not used in real life

 Absolute Design Rules

o Based on absolute distances (e.g. 0.75m)
o Tuned to a specific process (details usually

proprietary)
o Complex, especially for deep submicron
o Layouts not portable

Wires
All wire widths are
multiples of

metal 3

metal 2

metal 1

pdiff/ndiff

poly

Transistors
2

poly
3

diffusion
substra
te

2
3
1

All measures are multiples of

Vias
Types of via: metal1/diff, metal1/poly,

metal1/metal2.
4

4
1
2

Metal 3 via
Type: metal3/metal2.
Rules:
ocut: 3 x 3
ooverlap by metal2: 1
ominimum spacing: 3
ominimum spacing to via1: 2

Tub tie

4
1

Spacings
Diffusion/diffusion: 3
Poly/poly: 2
Poly/diffusion: 1
Via/via: 2
Metal1/metal1: 3
Metal2/metal2: 4
Metal3/metal3: 4