Burst Clock Controller

Kumar Gavanurmath

Agenda
What

is Burst clock.
Why Burst clock.
BCC Architecture. (Mentor)

BCC

Scan Burst is an innovative new at-speed DFT (Designfor-Test) tool from Logic Vision, designed specifically to
overcome the limitations of traditional at-speed DFT
techniques.

A technique to refine at-speed launch and capture

clock edge placement by applying several at-speed
shift cycles before the launch.

This reduces power droop and may make at-speed

edge placement more accurate during capture.

Extension to LOS.

Once the scan chains are fully loaded, the controller

shifts to the burst phase, in which the true functional
clocks are applied. The scan chains are still left in the
shift mode while the scan data rotates through the
scan chains for a few cycles. Then a single capture
cycle is applied and the data is shifted out

Why Burst?

The traditional approach of testing for performance

related defects with ATPG-based solutions has been to
generate patterns that target transition delay faults.

These patterns are applied using two at-speed

functional clock cycles to create a launch and
capture sequence. This approach is often referred to
as broadside or double-capture timing. This
technique, however, often lacks accuracy, resulting in
test escapes. In particular it suffers from what is
referred to as clock stretching.

This phenomenon is caused by the instantaneous drain

on power rails during the launch and capture cycles
that results in an increase of the clock period, an overly
and reduced delay fault detection.

Cont...

During the burst phase, all functional clocks are

enabled to produce a burst of clock cycles. The burst
is long enough to make sure that the supply has time
to stabilize before the launch and capture cycles.

Cont...

We can control how many at-speed shift cycles to be

slowed down during the burst phase (slowed down
cycles) and the spacing between the slowed down
pulses (effective slowed down frequency).

The number of at-speed burst cycles (burst length)

that a BCC will generate is fixed at the design time.

we should trade off these values with considerations

for power consumption, test time, and test quality.

Burst Clock Controller

The setup time at the input of the clock gating cell is a full
period (T) of the
clock input in the single clock case whereas it is half a period in
the synchronous clock group case.

Cont...

Once all scan chains are loaded, they are closed into
rotating segments & rotate at the true functional
speed, causing the needed at-speed activity before
the single capture cycle.

The number of clock cycles during the burst phase is

called the burst length. It defaults to 5 but can be
specified as small as two cycles.

A burst length of 5 cycles corresponds to four rotating

shift cycles followed by a single capture cycle. The
shift clock cycles during the Burst Mode can be
slowed down at run time to precisely tune the
instantaneous power level around the capture edge to
match the true worst case of instantaneous functional
power.

Detail Diagram of Clock

Controller

Shift Clock Controller(FSM)

Burst Mode Timing

Diagram

The benefits of the BurstMode

logic BIST architecture

True at-speed testing on all clock domains with both

logic BIST and ATPG patterns.
Complete short and long-term power management
Only one controller per layout region because there is
no need to further partition for power, true at-speed,
or clock speed binning requirements.

Implementation of timing
architecture

Reference
Embedded Test Hardware Reference
Software Version 2014.1
LV Flow Users Manual
Software Version 2014.1
https://www.google.co.in/patents/US7155651

Thank You