By

ECE
CHAMPIONS

INTRODUCTION
An integrated circuit (IC), also called a chip or
microchip, is a semiconductor wafer on which
thousands or millions of tiny resistors,
capacitors, and transistors are fabricated.
An IC can function as an amplifier, oscillator,
timer, counter, computer memory, etc.
A particular IC is categorized as linear (analog)
or digital, depending on its intended application.

INTRODUCTION(2)
Linear ICs have continuously varying output that
depends on the input signal level. The output
signal level is a linear function of the input signal
level.
Linear ICs are used as audio-frequency (AF)
and radio-frequency (RF) amplifiers. The
operational amplifier (op amp) is a common
device in these applications.

IC FABRICATION
The classifications of ICs based on fabrication
are monolithic ICs and hybrid ICs.
MONOLITHIC IC:A monolithic IC contains
active and passive devices (transistors, diodes,
resistors, capacitors) that are made in and on
the surface of a single piece of a single crystal
semiconductor, such as a Silicon (Si) wafer.

IC FABRICATION(2)
HYBRID IC: This IC is manufactured on an
insulating substrate utilizing some combination
of thick/thin film components, monolithic
semiconductors, and other discrete parts.
The substrate is alumina or ceramic wafer on
which a single or multiple layers of conductors,
resistors, and capacitors are deposited or
screened.

STEPS INVOLVED IN IC
FABRICATION
1.
2.
3.
4.
5.
6.
7.
8.
9.

Silicon wafer (substrate) preparation

Epitaxial growth
Oxidation
Photolithography
Diffusion
Ion implantation
Isolation technique
Metallization
Assembly processing & packaging

SILICON WAFER PREPARATION

Electronic-Grade Silicon (EGS) is the raw
material that is used for the preparation of
single-crystal silicon. EGS is a polycrystalline
material of high purity. EGS has some major
impurities like boron, carbon, and residual
donors.
The process starts by the production of
Metallurgical Grade Silicon (MGS) by charging it
with quartzite and carbon in an arc furnace.

SILICON WAFER
PREPARATION(2)
A phase change from solid, liquid, or gas phases
or crystalline solid phase occurs in growing
crystals. Czochralski growth is the process used
to grow most of the crystals from which silicon
wafers are produced.
INGOT TRIMMING AND SLICING: The crystal
got from the above process is trimmed and
sliced to a normal diameter of 100,125,150mm.

SILICON WAFER
PREPARATION(3)
The ingot is then sliced using a large-diameter
stainless steel saw blade with industrial
diamonds embedded into the inner-diameter
cutting edge to a size of 600 to 1000 micro
meter.
WAFER POLISHING AND CLEANING: When
the wafer is sliced, its surface will be heavily
damaged. This can be made normal by
polishing.

SILICON WAFER
PREPARATION(4)
After the wafer
polishing operations
are completed, the
wafers are thoroughly
cleaned, and dried.
Finally the wafers are
sawed into 100 to
8000 rectangular
chips of side 10 to
1mm

EPITAXIAL GROWTH
Epitaxial means growing a single crystal silicon
structure upon a original silicon substrate, so that the
resulting layer is an extension of the substrate
crystal structure.
The basic chemical reaction in the epitaxial
growth process of pure silicon is the hydrogen
reduction of silicon tetrachloride.
1200oC
SiCl+ 2H <-----------> Si +4HCl

EPITAXIAL GROWTH(2)
Epitaxial growth is of 2 types homo epitaxy and
hetero epitaxy.
If both crystals are of the same material, the
process is known as homo epitaxy. If the
materials are different, it is known as hetero
epitaxy.

EPITAXIAL GROWTH(3)
This process is carried out in a reaction chamber
consisting of a long cylindrical quartz tube
encircled by RF induction coil.
The silicon wafers are placed on a rectangular
graphite rod called boat which is placed in
reaction chamber.
In the reaction chamber graphite is heated to a
temperature of 1200C.

EPITAXIAL GROWTH(4)
The gases required for the growth of epitaxial layers are
introduced into the reaction chamber through control
console.

OXIDATION
It is the process to prevent the diffusion of
impurities using SiO2.
The SiO2 layer acts as a hard protective coating
and stands against any contamination.
By selectively etching SiO2 windows can be
formed to fabricate various components.

OXIDATION(2)
The silicon wafers are stacked up in a quartz
boat and then inserted into quartz furnace tube.
The Si wafers are raised to a high temperature
in the range of 950 to 1150 o C and at the same
time, exposed to a gas containing O2 or H2O or
both.
The chemical action is
Si + 2HO -----------> Si O2+ 2H2

PHOTOLITHOGRAPHY
The process of photolithography makes it
possible to produce microscopically small circuit
and device pattern on Si wafer. It determines
the geometric features specified by the layout as
the integrated circuit is fabricated layer by layer.
The conventional photolithography uses ultraviolet
light exposure.
Two processes involved in photolithography are
making a photographic mask, photo etching

PHOTOLITHOGRAPHY(2)
PHOTO MASK :The development of photo mask
involves the preparation of initial artwork and
reduction. It does not allow deposition ,diffusion
and fabrication process.
A photo mask, containing pattern information in
the form of an etched chromium layer on glass,
is prepared for each layer. An image of the photo
mask is projected onto the surface of the silicon
wafer

PHOTOLITHOGRAPHY(3)
ETCHING: Etching is used to remove material
selectively in order to create patterns.
The pattern is defined by the etching mask,
because the parts of the material, which should
remain, are protected by the mask.
The unmasked material can be removed either
by wet (chemical) or dry (physical) etching.

PHOTOLITHOGRAPHY(4)
Wet etching is strongly isotropic which limits its
application and the etching time control is
difficult. Wet etching is not suited to transfer
patterns with sub-micron feature size.
Wet etching has a high selectivity (the etch rate
strongly depends on the material) and it does
not damage the material. Dry etching is highly
anisotropic but less selective. It is more capable
for transfering small structures

DIFFUSION
Diffusion is the movement of impurity atoms in a
semiconductor material at high temperatures.
A quartz boat containing cleaned wafers is
pushed into a hot zone at the temperature of
1000.
A carrier gas like oxygen, nitrogen is used to
sweep the impurity to high temperature zone.

DIFFUSION(2)
The depth of the diffusion depends on the time
of diffusion.
Diffusion takes place both laterally and vertically.
Diffusion is used to form the source, drain, and
channel regions in a MOS transistor. The main
disadvantage is that it may damage the
substrate due to high temperature.

ION IMPLANTATION
This process is an alternative to diffusion
process. In this process high beam of high
energy dopant ions are accelerated and allowed
to penetrate the silicon wafer.
The depth of penetration of ion increases with
increasing accelerating voltage. The main
advantage is that this process takes place at low
temperature which prevents lateral spreading of
diffused regions.

ISOLATION TECHNIQUE
In IC it is necessary to provide electrical isolation
between different components and
interconnections.
The two commonly used techniques are p-n
junction isolation and dielectric isolation.
P-N JUNCTION ISOLATION: In this p type
impurities are diffused into n type epitaxial layer.

ISOLATION TECHNIQUE(2)
In dielectric isolation, a layer of solid dielectric
such as SiO2 or ruby completely surrounds each
components thereby producing isolation, both
electrical and physical.
This isolating dielectric layer is thick enough so
that its associated capacitance is negligible.
Also, it is possible to fabricate both PNP and
NPN transistors within the same silicon
substrate.

METALLIZATION
The process of producing a thin metal film layer
that will serve to make interconnection of the
various components on the chip is called
metallization.
Metallization takes place towards the end of the
fabrication process and involves the deposition
of a thin layer of aluminium over the whole of the
wafer and then the use of photolithography to
define the interconnect pattern.

METALLIZATION(2)
Aluminium is preferred for
metallization.
It is a good conductor.
It makes good mechanical
bonds with silicon.
It forms a low resistance
contact.
It can be applied and patterned
with a single deposition and
etching process.

ASSEMBLY PROCESSING AND

PACKAGING
Each of the wafer processed contains several
hundred chips. So these chips are separated
and packaged by a method called scribing and
cleaving.
This method uses a diamond tipped tool to cut
lines along the rectangular grid separating the
individual chips.

ASSEMBLY PROCESSING AND

PACKAGING(2)
There are three
package
configurations
available they are
metal can package,
ceramic flat
package, dual in
line package.