Professional Documents
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Bits Rit
Bits Rit
practically oriented science with very high peaks that few can scale
Working professionals in industry are at different levels of height in
terms of expertise
High-end expertise is to be found only in very small pockets within
the industry and academia across the globe
Due to fast pace of innovation, Industry and Academia need to come
closely together for pursuing Applied Research
At BITS-RIT APEX Center, we will attempt to bring together top
experts from industry and academia to help the working
professionals attain global heights in professional excellence
Applied research will be a key focus through close collaboration with
industry and top academic institutions
RAMLAB
Goals
Applied Research
Education
RAMLAB
Bangalore
To upgrade skills of VLSI professionals and managers to the
world-class level
Offered by the best faculty members and industry professionals
from India and across the world
OLAB extension will be set up at the center in Bangalore with
state-of-the-art EDA tools
Offered to professionals from Center Affiliates companies
The program will consist of multiple courses and access to OLAB
Each course will be a complete unit in itself with appropriate credits
awarded from BITS - Pilani
Accumulation of enough credits and completion of a thesis will entitle
for a masters degree from BITS
Will be taught by some of the best faculty and Industry professionals
from India and abroad
RAMLAB
BITS-RIT Collaboration
BITS will take ownership in setting up the center, the labs, the equipment
and the management responsibilities for the center. All investments towards
this will come from BITS
BITS will also drive the Professional Excellence Program with involvement
from faculty from RIT as well as from across the world
Award of degrees / certificates for Professional Excellence programs will be
managed by BITS
RIT will play the lead role in Applied Research, particularly in the area of RF,
Analog and Mixed Signal Design with involvement from BITS faculty and
others in Industry
Prof. P. R. Mukund, Director RAMLAB at RIT will be visiting Bangalore often
to supervise the research programs.
At least one or more research associates from RAMLAB of RIT will be
located in Bangalore to carry on with the applied research work.
PhD degrees may be awarded by RIT and BITS jointly or separately
depending on the nature of association of the lead researchers
BITS and RIT will jointly promote the center
RAMLAB
Course Structure
Each course will normally be about 20-30 people and will
have a tuition fee of about INR 10K 30K per course per
student (including access to OLAB as well)
These courses will be offered as
RAMLAB
Corporate Sponsors
Each interested company will become a Corporate Sponsor for the
Center with an annual fee of INR 75K INR 200K based on their
employee strength
Corporate Sponsors will also be able to provide input on courses
offered and choice of faculty members
Corporate Sponsors will ensure that the Center remains world class
and dynamic
Annual Corporate Sponsorship Fee
Employee Strength < 50
: INR 75K
Employee Strength 50-100
: INR 125K
Employee Strength > 100
: INR 200K
RAMLAB
RAMLAB
Hours
Lab
18
No
30
Yes
30
Yes
30
Yes
30
Yes
15
No
30
Yes
30
Yes
RAMLAB
Hours
Lab
15
Yes
15
Yes
30
Yes
15
Yes
15
No
15
Yes
RF Design
30
Yes
15
No
15
Yes
RAMLAB
Hours
Lab
30
Yes
30
Yes
30
Yes
30
Yes
RAMLAB
Software Testing
Technical Writing
Embedded SW development
Bio-Technology
RAMLAB
RAMLAB
expertise gained
Possible avenue for better employee retention
Compelling cost structure to try new ideas
Excellent design infrastructure
Instant access to university expertise on
fundamental knowledge
RAMLAB
RAMLAB
RAMLAB
RAMLAB
Open Silicon
Mentor Graphics
CADENCE
SUN
Microsystems
WIPRO
OLAB FACILITIES
OLAB ACTIVITIES
Students of M.E. Microelectronics for
conducting
laboratory sessions
Students of First Degree Programme
for courses
in the area of VLSI Design
To Facilitate Research activities
To conduct short term courses for
Industry
Professionals
To support entrepreneurs in
Technology
Master/Controller module
Sensor/Slave module
Processor
Host I/F
Processor
&
Peripherals
Analog
interface
Circuits
(ADC/DAC)
RF Circuitry
(Wireless
transceivers)
RF Circuitry
(Wireless
transceivers)
Sensors
interface
Circuits
Sensor/Slave module
Processor
RF Circuitry
(Wireless
transceivers)
Sensors
interface
Circuits
RAMLAB - Overview
Semiconductor Research
Corporation
Technology Used:
Intel Corporation
Research Faculty
0.25 um TSMC
Graduate Students
CMOS
0.25 um IBM CMOS
Distinguished Researcher
Harris
Corporation
Equipment:
Unix Workstations with Cadence
Suite
ATE with probe station, spectrum
analyzer & Network Analyzer for RF
Characterization
Industry Liaisons
Ph.D. Students
Anand Gopalan
Sripriya Bandi
Tejasvi Das
National Science
Foundation
Sharmila Sridharan
Mark Pude
Jeff Lillie
Eastman Kodak
Company
Kawasaki LSI
LSI Logic
RAMLAB
Microsystems
Systems
RAMLAB
R1
LD
M3
R2
LG
M2
M1
LS
LNA Schematic
RAMLAB
Chip-Package Co-Design
Accomplishments
Circuit Components Designed and
Fabricated using IBMs 0.25um
CMOS
Low Noise Amplifier
Single Balanced Mixer
Low Phase Noise VCO
RAMLAB
A/D and
Op-Amp
Analysis
Design Methodologies
RF
Modules
Passive
Characterization
Horizontal
Floor Planning
Digital
Modules
RF Design
Digital Logic
Vertical
MEMS
Integration
Quality Factor
Novel Design
Techniques
RF
Inductor
Library
40
L1 of f chip
L2 of f chip
L1 on chip
L2 on chip
35
30
Power
Distribution
25
20
15
10
5
Frequency(GHz)
0
0
Inductor Libraries
for RF Design
Inductor Modeling
and Characterization
Vertically Integrated Designs
(Si on Si)
RAMLAB
Pin Functionality,
RF Circuit
Package
RLC Models
Krylovs
Sub Space
Models
Application
Specific Reduced
Order Models
RFIC Design
Model Reduction for power pin
Lw
Original
curve
Order: 27
Order = 5
Original curve
Order = 27
Rg
Lg
SiP Design
Methodology
Order: 7
Cg
Order = 6
Order: 6
Order: 5
G. Nayak, C. Washburn, P.R. Mukund, System in a Package Design of a RF Front End System using
Application Specific Reduced Order Models ,Accepted at the 18th International Conference on VLSI Design
and 4th International Conference on Embedded Systems, Calcutta, India, January 2005
RAMLAB
RAMLAB
Si
Die
RF Design
CHI
P
Bond Wire
CHIPCARRIER
RAMLAB
DESIGN FEATURES
Sensing Resistor 7
Feedback structure
Reduction in number of Gain
Addition of bypass capacitor
Stages
RAMLAB
RAMLAB
Self-Calibrating RF circuits
Inability to probe RFICs
directly
Probe
s
Si
Die
RF Design
RF
Testing
High Cost $$
Limitations of Co-Design
Package portability
Time Intensive
Use of DSPs
Can detect
but not
correct faults
RAMLAB
Self-Calibration: Methodology
Sense
Amplifier
Start with
nominal RF ckt
Sense current
with minimally
intrusive
element
Peak Detector
Amplify sensed
current
Down-convert
signal to
baseband
Map signal to
performance
metric
RF CIRCUIT
Dynamically modify
design parameters in
RF circuit
Generate
baseband/digital
signal to modify
design parameters
NO
Baseband
Signal
Processing
Performanc
e metric
ok?
YES
3
End
Calibration
process
Self-correction on-the-fly
Baseband processing
Low overheads
RAMLAB
Self-Calibration: Results
S11 curves before
and after
calibration.
(a) when a parasitic
inductance of
1nH is added.
(b) when CGS of the
LNA transistor is
reduced by
10%.
S11 curves before and after calibration for the
weakest corner:
Ideal S11=1.824 GHz
Parasitic inductance shifted it to 1.728 GHz
After calibration the input match aligned
itself at 1.817 GHz
RAMLAB
RAMLAB
RAMLAB
Thank You
RAMLAB