Professional Documents
Culture Documents
Lesson 4: Synchronous Design Architectures: Data Path and High-Level Synthesis (Part Two)
Lesson 4: Synchronous Design Architectures: Data Path and High-Level Synthesis (Part Two)
Sept. 2005
Topics
Data Subsystem.
High-level Synthesis
Scheduling
Allocation
Sept. 2005
1. Data Subsystem
It consists of:
Storage modules, such registers;
Functional modules (operators);
Buses, composed of switches and wires connecting
storages and functional modules;
Control points, which are points where control signals
are connected; and
Condition points, which are corresponding to output
signals used by the control subsystem.
Sept. 2005
Sept. 2005
Register File
Sept. 2005
Sept. 2005
Functional Modules
Functional Modules (operators) perform
transformations on bit-vectors.
An operator is specified by the names of input
and output vectors, and the name of the function
performed by the operator.
Operators can perform several operations as
specified by operation-selection inputs.
Sept. 2005
CASE op_sel IS
WHEN F1 => z_out <= x_in op1 y_in AFTER delay;
WHEN F2 => z_out <= x_in op2 y_in AFTER delay;
....
END CASE;
Sept. 2005
Buses
Buses provide connection between components
in the system. They consist of:
Direct connections, also called wires, links, or lines;
and
Switches to enable the connections.
Sept. 2005
Sept. 2005
Sept. 2005
Type of buses
Complete connection, called crossbar, in which
m simultaneous transfers are possible.
Single interconnection, which allows only one
source to be connected at the bus at a time.
Sept. 2005
Sept. 2005
Sept. 2005
Sept. 2005
Sept. 2005
2. High-level Synthesis
High-level synthesis also know as behavioral
synthesis constructs a register-transfer from a
behavior in which the times of operations are not
fully specified.
High-level synthesis methods help us
understand the design space and come up with
a design that meets all our requirements.
This technique is particularly useful in FPGA
Rapid Prototyping.
The primary jobs in translating a behavior
specification into architecture are scheduling and
allocation (binding).
Sept. 2005
Sept. 2005
Sept. 2005
Sept. 2005
Sept. 2005
Data dependencies
Data dependencies describe relationships
between operations:
x <= a + b; value of x depends on a, b
Sept. 2005
Sept. 2005
single-assignment form:
x1 <= a + b;
y <= a * c;
z <= x1 + d;
x2 <= y - d;
x3 <= x2 + c;
Sept. 2005
Sept. 2005
Sept. 2005
registers fall on
clock cycle
boundaries
Sept. 2005
Register lifetimes
a
Sept. 2005
Sept. 2005
muxes allow
function units
to be shared
for several
operations
Sept. 2005
Sept. 2005
Sept. 2005
Finding schedules
Two simple schedules:
As-soon-as-possible (ASAP) schedule puts every
operation as early in time as possible.
As-late-as-possible (ALAP) schedule puts every
operation as late in schedule as possible.
Sept. 2005
ASAP
ALAP
Sept. 2005
Sept. 2005
Sept. 2005
Sept. 2005
Operator chaining
May execute several operations in
sequence in one cycleoperator
chaining.
Delay through function units may
not be additive, such as through
several adders.
Sept. 2005