About Myself

Masters Program

Masters in Electrical Engineering at UMN, Twin Cities specializing

in VLSI Design.

Fall15 Courses - VLSI Design, Advanced Computer Architecture and

Applied Parallel Programming

Current courses - Advanced VLSI Design, VLSI Design Automation ,

VLSI Design Lab

Planned courses - Advanced Verification Techniques, Algorithms

and Data structures

Schematic and Mask Layout of 16bit

Knowles Tree Adder

Design and Layout of 16bit Knowles tree adder with NCSU 45nm FreePDK

Tools Used

Cadence Virtuoso Schematic and Layout editor

Hspice Circuit Simulation

Cosmoscope Waveform analysis

Optimization Techniques

Inserted buffers in the worst case path.

To drive a large load at the output the size of last stage inverter was increased 2X
times

Folded inverter design was used to minimize area.

Schematic and Mask Layout of 16bit

Knowles Tree Adder - continue

Grid layout technique

Easier routing between blocks

Minimum area.

Metal1 - Internal routing of blocks

Metal2 - Vertical routing

Metal3 - Horizontal routing

Metal4 and Metal5 - Power grids

Added as much as contacts in the drain and source junction of PMOS and
NMOS transistors to increase the current density.

Distribution of adder delay at 1.1V, 110C

Final Layout of 16bit Knowles tree Adder

Operating frequency: 949MHz; Power: 372uW; Area: 178 sq.um

Adaptive Insertion Policies for High

Performance Caching

Memory-intensive workloads with bigger working set than the cache size are
benefitted with this policy

Policy to dynamically switch between LRU and BIP

Studied MPKI for all policies on various benchmarks.

Benchmarks Anagram, GCC, Gzip, Go, Art

Static and Dynamic Power consumption comparison done.

Simulator used

Simple scalar - Architectural simulator

WATTCH - Power Analysis

Advanced MRI Reconstruction using

CUDA in NVIDIA GTX480

LOST Algorithm an efficient technique for MRI Reconstruction system, was

accelerated using CUDA

Used parallel algorithmic techniques

Shared memory

Memory coalescing

Obtained 20x speed-up over CPU version

The time consuming FFT and IFFT were implemented using inbuilt CUDA
library functions cufft and cuifft

Schematic and Mask Layout of 128kb 2k x 64b

SRAM with NCSU 45nm FreePDK (Ongoing)

Full Schematic and Layout design of 128 kb SRAM using Cadence Virtuoso

Target Requirements

Power Management

Minimum area

Maximum Read and Write Noise margins

Replacing pessimistic way of computing Read and Write SNM by dynamic

method

Designed Sleep circuit - To reduce the static power during sleep mode.

Designed Write Assist circuit(TVC-WA) - Based on Intel JSSC13 Paper

Other Ongoing Projects

Verilog implementation of Coherent Cache system using MOESI protocol

Design includes - Multi core processor system with Memory and Bus
Controllers.

Formal equivalence checking on RTL and netlist implementation of MOESI

cache coherence protocol.

The equivalence checking will be performed using Synopsyss Formality Ultra

tool

Undergraduation

I joined Anna University, College of Engineering, Guindy campus to do my

Bachelors in Electronic and Communication Engineering.

Major courses - CMOS Analog IC design, Advanced Digital Signal Processing,

etc

Undergrad project
Implementation of smoke detecting algorithm using Altera Cyclone II FPGA
device.
-

High speed image processing capability of FPGA is exploited for early detection

Graduated in May 13

Work Experience

2 years of work experience as an Application developer in IBM, India Pvt. Ltd.

Responsible for maintaining the test environments for system testing.

Key deliverables include maintaining and enhancing the framework for test
environments within resource budgets.

Awarded the The Best of IBM for my outstanding performance for

automating the standards 2014 project test cases.

Best of IBM Award

Thank You