Lecture 11:

Sequential
Circuit
Design

Outline

Sequencing
Sequencing Element Design
Max and Min-Delay
Clock Skew
Time Borrowing
Two-Phase Clocking

CMOS VLSI Design 4th Ed.

11: Sequential Circuits2

Sequencing
Combinational logic
output depends on current inputs
Sequential logic
output depends on current and previous inputs
Requires separating previous, current, future
Called state or tokens
Ex: FSM, pipeline
clk

in

CL

Finite State Machine

clk

out

clk

CL

clk

CL

Pipeline

CMOS VLSI Design 4th Ed.

11: Sequential Circuits3

Sequencing Cont.
If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
Ex: fiber-optic cable
Light pulses (tokens) are sent down cable
Next pulse sent before first reaches end of cable
No need for hardware to separate pulses
But dispersion sets min time between pulses
This is called wave pipelining in circuits
In most circuits, dispersion is high
Delay fast tokens so they dont catch slow ones.
CMOS VLSI Design 4th Ed.

11: Sequential Circuits4

Sequencing Overhead
Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
Inevitably adds some delay to the slow tokens
Makes circuit slower than just the logic delay
Called sequencing overhead
Some people call this clocking overhead
But it applies to asynchronous circuits too
Inevitable side effect of maintaining sequence

CMOS VLSI Design 4th Ed.

11: Sequential Circuits5

Sequencing Elements

Flop

Latch

Latch: Level sensitive

a.k.a. transparent latch, D latch
Flip-flop: edge triggered
A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams
clk
clk
Transparent
D
Q
D
Q
Opaque
Edge-trigger
clk
D
Q (latch)
Q (flop)

CMOS VLSI Design 4th Ed.

11: Sequential Circuits6

Latch Design
Pass Transistor Latch
Pros
+ Tiny
+ Low clock load
Cons
Vt drop
nonrestoring
backdriving
output noise sensitivity
dynamic
diffusion input

Used in 1970s

CMOS VLSI Design 4th Ed.

11: Sequential Circuits7

Latch Design
Transmission gate
+ No Vt drop

- Requires inverted clock

CMOS VLSI Design 4th Ed.

11: Sequential Circuits8

Latch Design
Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
Output noise sensitivity
Or diffusion input
Inverted output

CMOS VLSI Design 4th Ed.

11: Sequential Circuits9

Latch Design
Tristate feedback
+ Static
Backdriving risk

Static latches are now essential

because of leakage

CMOS VLSI Design 4th Ed.

11: Sequential Circuits

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Latch Design
Buffered input
+ Fixes diffusion input
+ Noninverting

CMOS VLSI Design 4th Ed.

11: Sequential Circuits

11

Latch Design
Buffered output
+ No backdriving

Widely used in standard cells

+ Very robust (most important)
- Rather large
- Rather slow (1.5 2 FO4 delays)
- High clock loading

CMOS VLSI Design 4th Ed.

11: Sequential Circuits

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Latch Design
Datapath latch
+ smaller
+ faster
- unbuffered input

CMOS VLSI Design 4th Ed.

11: Sequential Circuits

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Flip-Flop Design
Flip-flop is built as pair of back-to-back latches

CMOS VLSI Design 4th Ed.

11: Sequential Circuits

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Enable
Enable: ignore clock when en = 0
Mux: increase latch D-Q delay
Clock Gating: increase en setup time, skew
Symbol

Multiplexer Design

Clock Gating Design

en

1
0

en

en

1
0

Q
D

en

Flop

Flop

Flop

en

Latch

Latch

Latch

en

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Reset
Force output low when reset asserted
Synchronous vs. asynchronous

reset
Synchronous Reset

reset
D

reset

reset
D

Flop

Symbol

Latch

Asynchronous Reset

reset

reset
D

reset

reset

CMOS VLSI Design 4th Ed.

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Set / Reset
Set forces output high when enabled
Flip-flop with asynchronous set and reset

reset

set
D

set

reset

CMOS VLSI Design 4th Ed.

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Sequencing Methods
clk
clk
Flop

clk
Flop

Combinational Logic

tnonoverlap

2
Combinational
Logic
Half-Cycle 1

1
Combinational
Logic

Latch

Half-Cycle 1

tpw
p
Combinational Logic

CMOS VLSI Design 4th Ed.

Latch

p
Latch

Pulsed Latches

tnonoverlap

Tc/2

Latch

2-Phase Transparent Latches

Latch

Flip-Flops

Flip-flops
2-Phase Latches
Pulsed Latches

Tc

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Timing Diagrams
Contamination and
Propagation Delays
Combinational
Logic

Logic Prop. Delay

tcd

Logic Cont. Delay

tpcq

Latch/Flop Clk->Q Prop. Delay

tccq

Latch/Flop Clk->Q Cont. Delay

tpdq

Latch D->Q Prop. Delay

tcdq

Latch D->Q Cont. Delay

tsetup

Latch/Flop Setup Time

thold

Latch/Flop Hold Time

tpd

Y
Y

clk

clk
Flop

tpd

A
tcd

tsetup

thold

D
tpcq
Q

clk

Latch

clk
D

tccq

tccq

tsetup
tpcq

tcdq

thold
tpdq

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Max-Delay: Flip-Flops
clk
Q1

Combinational Logic

D2

F2

sequencing overhead

clk
F1

t pd Tc tsetup t pcq
1 42 43

Tc
clk
Q1

tsetup

tpcq
tpd

D2

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Max Delay: 2-Phase Latches

D1

sequencing overhead

Q1

Combinational
Logic 1

D2

1
Q2

Combinational
Logic 2

D3

L3

pdq

2
L2

122t 3

L1

t pd t pd 1 t pd 2 Tc

Q3

1
2
Tc
D1
Q1

tpdq1
tpd1

D2

tpdq2

Q2

tpd2

D3

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Max Delay: Pulsed Latches

D1

sequencing overhead

p
Q1

D2

Combinational Logic

L2

p
L1

t pd Tc max t pdq , t pcq tsetup t pw

1 4 4 4 4 2 4 4 4 43

Q2

Tc
D1
(a) tpw > tsetup

tpdq

Q1

tpd

D2
p
tpcq

Tc
tpd

Q1

tpw
tsetup

(b) tpw < tsetup

D2

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Min-Delay: Flip-Flops
clk
F1

tcd thold tccq

Q1

CL

D2

F2

clk

clk
Q1 tccq
D2

tcd
thold

CMOS VLSI Design 4th Ed.

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Min-Delay: 2-Phase Latches

1
L1

tcd 1,tcd 2 thold tccq tnonoverlap

CL

D2

Paradox: hold applies

twice each cycle, vs.
only once for flops.

L2

Hold time reduced by

nonoverlap

But a flop is made of

two latches!

Q1

tnonoverlap

tccq

2
Q1
D2

tcd
thold

CMOS VLSI Design 4th Ed.

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Min-Delay: Pulsed Latches

p
Q1

CL

p
D2

L2

Hold time increased

by pulse width

L1

tcd thold tccq t pw

tpw
thold

Q1 tccq

tcd

D2

CMOS VLSI Design 4th Ed.

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Time Borrowing
In a flop-based system:
Data launches on one rising edge
Must setup before next rising edge
If it arrives late, system fails
If it arrives early, time is wasted
Flops have hard edges
In a latch-based system
Data can pass through latch while transparent
Long cycle of logic can borrow time into next
As long as each loop completes in one cycle
CMOS VLSI Design 4th Ed.

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Time Borrowing Example

1
2

Combinational Logic

Borrowing time across

half-cycle boundary

Combinational
Logic

Borrowing time across

pipeline stage boundary

2
Combinational Logic

Latch

(b)

Latch

1
Latch

2
Latch

(a)

Latch

Combinational
Logic

Loops may borrow time internally but must complete within the cycle

CMOS VLSI Design 4th Ed.

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How Much Borrowing?

D1

L1

tborrow

T
c tsetup tnonoverlap
2

2
Q1

Combinational Logic 1

D2

L2

2-Phase Latches

Q2

Pulsed Latches

tnonoverlap

tborrow t pw tsetup

Tc
Tc/2
Nominal Half-Cycle 1 Delay

tborrow

tsetup

D2

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Clock Skew
We have assumed zero clock skew
Clocks really have uncertainty in arrival time
Decreases maximum propagation delay
Increases minimum contamination delay
Decreases time borrowing

CMOS VLSI Design 4th Ed.

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Skew: Flip-Flops
Combinational Logic

D2

Tc
clk

tcd thold tccq tskew

tpcq
Q1

tskew
tpdq

tsetup

D2

F1

clk
Q1

CL

clk
D2

F2

sequencing overhead

Q1

F1

t pd Tc t pcq tsetup tskew

1 4 44 2 4 4 43

clk
F2

clk

tskew
clk

thold

Q1 tccq
D2

tcd

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Skew: Latches
Q1

Combinational
Logic 1

D2

1
Q2

Combinational
Logic 2

D3

Q3

pdq

sequencing overhead

tcd 1 , tcd 2 thold tccq tnonoverlap tskew

tborrow

L3

122t 3

D1

L1

t pd Tc

L2

2-Phase Latches

Tc
tsetup tnonoverlap tskew
2

Pulsed Latches

t pd Tc max t pdq , t pcq tsetup t pw tskew

1444442444443
sequencing overhead

tcd thold t pw tccq tskew

tborrow t pw tsetup tskew
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Two-Phase Clocking
If setup times are violated, reduce clock speed
If hold times are violated, chip fails at any speed
In this class, working chips are most important
No tools to analyze clock skew
An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times
Call these clocks 1, 2 (ph1, ph2)

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Safe Flip-Flop
Past years used flip-flop with nonoverlapping clocks
Slow nonoverlap adds to setup time
But no hold times
In industry, use a better timing analyzer
Add buffers to slow signals if hold time is at risk

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Adaptive Sequencing
Designers include timing margin
Voltage
Temperature
Process variation
Data dependency
Tool inaccuracies
Alternative: run faster and check for near failures
Idea introduced as Razor
Increase frequency until at the verge of error
Can reduce cycle time by ~30%
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Summary
Flip-Flops:
Very easy to use, supported by all tools
2-Phase Transparent Latches:
Lots of skew tolerance and time borrowing
Pulsed Latches:
Fast, some skew tol & borrow, hold time risk

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