Essential components of a

microcontroller

CISC Vs RISC
FEATURES

CISC

RISC

Architecture

Harvard/Von
neumann

Mostly
harvard

Instructions

Are like C-macros

Simpler

Variable length

Fixed length

Instruction set

Non orthogonal

Orthogonal

GPRs

Limited

Large

Operations

Reg/Mem

Only on reg

Pipeling

No

Yes

Silicon usage

More

less

Harvard v/s Von Neumann

In Harvard volatile and non-volatile
are treated as separate systems
each with its own address and
database.
It allows simultaneous access to the
program and data memories.
Principle advantage is efficiency

Von Neumann
It is also called Princeton architecture
It is a single memory system
Only one set of address covers both
the volatile and non-volatile
memories
Less efficient ,several memory cycles
are needed
Simpler system no access difference
between constant and variables

MSP 430 (mixed signal

processor)
IT is a 16 bit micro controller
developed by TI.
Designed for low power applications.
Reduced Instruction Set Computer
Architecture
27 instructions
Uses Von Neumann architecture to
connect CPU peripherals and buses

Features of MSP430
The CPU is small and efficient, with a large
number of registers.
It is extremely easy to put the device into a
low-power mode. No special instruction is
needed: The mode is controlled by bits in
the status register. The MSP430 is
awakened by an interrupt and returns
automatically to its low-power mode after
handling the interrupt.
There are several low-power modes,
depending on how much of the device
should remain active and how quickly it

Contd..
There is a wide choice of clocks.
Typically, a low-frequency watch
crystal runs continuously at 32 KHz
and is used to wake the device
periodically. The CPU isclocked by an
internal, digitally controlled oscillator
(DCO), which restarts in less than 1s
in the latest devices. Therefore the
MSP430 can wake from a standby
mode rapidly, perform its tasks, and

Contd..
A wide range of peripherals is
available, many of which can run
autonomously without the CPU for
most of the time.
Many portable devices include liquid
crystal displays, which the MSP430
can drive directly.

Family of MSP430
MSP430x1xx: Provides a wide range of
general-purpose devices from simple
versions to complete systems for processing
signals. Packages have 2064 pins.
MSP430F2xx: A newer, general-purpose
family introduced in 2005. Its CPU can
run at 16 MHz, double the speed of earlier
devices, while consuming only half the
current the same speed. Some come in 14pin packages.

Contd..
MSP430x3xx: The original family,
which includes drivers for LCDs.
It is now obsolescent.
MSP430x4xx: Can drive LCDs
with up to 160 segments. Many
of them are ASSPs, but there are
general-purpose devices as well.
Their packages have 48113 pins,
many of which are needed for the
LCD.

Example

The Outside ViewPinOut

The F2013 is available in a traditional
14-pin plastic dual-in-line package
(PDIP) with pins 0.1 apart.

The Inside ViewFunctional

Block Diagram

Ordering of bits, bytes, and words in memory, adapted

from the
MSP430x2xx Family Users Guide. Addresses increase
up the page.

 There are two ways in which these two

bytes can be stored in the two bytes of a
word in memory and both are in use.
Little-endian ordering: The low-order
byte is stored at the lower address
and the high-order byte at the higher
address. This is used by the MSP430 and
is the more common format.
Big-endian ordering: The high-order
byte is stored at the lower address.
This is used by the Freescale HCS08

Memory Map

Registers in the CPU of the

MSP430.

Program Counter (PC)

This contains the address of the next instruction
to be executed
The usual cycle of execution is that the contents
of the PC are placed on the address bus and the
next instruction is fetched from this address.
The value in the PC is automatically increased
by 2 after each fetch so that it is ready for the
next word
Subroutines and interrupts also modify the PC
but in these cases the previous value is saved
on the stack and restored later.

Stack Pointer (SP)

When a subroutine is called the CPU must
jump to the subroutine, execute the code
there, and finish by returning to the
instruction after the call.
It must therefore keep track of the contents
of the PC before jumping to the subroutine
so that it can return afterward. This is done
with a stack, which is also known as a last
infirst out (LIFO) data structure
Disadvantage of stack-only return addresses

Stack operation

Status Register (SR)

This contains a set of flags (single bits)
The C, Z, N, and V bits are affected by many of the
operations performed by the ALU
carry bit C :the result of an arithmetic operation is
too large to fit in the space allocated.
The hexadecimal sum 0x75+0xC7=0x13C, where the
result is too large to be held in a single byte. The
processor would put 0x3C in the destination and set
the carry bit to show that the result had overflowed

Status Register (SR)

The zero flag Z is set when the result of
an operation is 0.
To check whether two values are equal:
They are subtracted and the Z bit is
tested to see whether the result is 0,
which shows that the values are the same
The negative flag N is made equal to the
msb of the result, which indicates a
negative number if the values are signed.

Status Register (SR)

The signed overflow flag V is set when the result of a signed
operation has overflowed
This flag is important if you are performing calculations with signed
numbers
Consider the following calculation:
0111 1111 1111 1111 (hex 7fff or decimal 32767)
+ 0000 0000 0000 0001
================
1000 0000 0000 0000 (hex 8000 or decimal +/- 32768)
The MSB in this case is a 1 which, depending on context and your
application may indicate that this is a negative number. This makes
no sense however as the addition of two positive numbers can never
produce a negative result.
The V flag is set in this case as a warning of the possible
misinterpretation of the sign of this number.

Status Register (SR)

Enable Interrupts: Setting the general interrupt
enable or GIE bit enables maskable interrupts
Control of Low-Power Modes: The CPUOFF,
OSCOFF, SCG0, and SCG1 bits control the mode
of operation of the MCU
All systems are fully operational when all bits
are clear
Setting combinations of these bits puts the
device into one of its low-power modes

Status register

Constant Generators
Both R2 and R3 are used to provide
the 6 most commonly used constants
This saves storing the values in the
program and having to fetch them
each time
The operation depends on the
addressing modes

Addressing Modes
A key feature of any CPU is its range
of addressing modes
The MSP430 has four basic modes
These modes are made more useful
by the way in which they interact
with the CPUs registers

Addressing Modes
Double operand : Arithmetic and
logical operations with two operands
such as
add.w src, dst
Single operand : A mixture of
instructions
for
control
or
to
manipulate a single operand
Jumps: The jump to the destination

Register Mode
Register mode operations work
directly on the processor registers,R4
through R15, or on special function
registers, such as the
program counter or status register.
They are very efficient in terms of
both instruction speed and code
space

Register Mode
Example 1: Move (copy) the contents of source
(register R4) to destination (register R5). Register R4 is
not affected.

Before operation: R4=A002h

R5=F50Ah PC = PCpos
Operation: MOV R4, R5
After operation: R4=A002h R5=A002h
PC = PCpos + 2

Indexed mode
The Indexed mode commands are
formatted as X(Rn), where X is a
constant and Rn is one of the CPU
registers.
The absolute memory location X+Rn
is addressed.
Indexed mode addressing is useful
for applications such as lookup
tables.

Indexed mode
Example 2: Move (copy) the contents at source
address (F000h +R5) to destination (register R4).

Before operation: R4=A002h

R5=050Ah Loc:0xF50A=0123h
Operation: MOV F000h(R5), R4
After operation: R4=0123h
R5=050Ah Loc:0xF50A=0123h

Symbolic mode
Symbolic mode allows the
assignment of labels to fixed memory
locations
so that those locations can be
addressed.
This is useful for the development of
embedded programs

Symbolic mode
Example 3: Move the content of source
address XPT (x pointer) to the destination address
YPT (y pointer).

Before operation: XPT=A002h

Location YPT=050Ah
Operation: MOV XPT, YPT
After operation: XPT= A002h
Location YPT=A002h

Indirect register mode

The data word addressed is located
in the memory location pointed to by
Rn.
Indirect mode is not valid for
destination operands, but
can be emulated with the indexed
mode format 0(Rn).

Indirect register mode

Example 5: Move the contents of the source
address (contents of R4) to the destination
(register R5). Register R4 is not modified.
Before operation: R4=A002h
R5=050Ah Loc:0xA002=0123h
Operation: MOV @(R4), R5
After operation: R4= A002h
R5=0123h Loc:0xA002=0123h

Indirect auto increment

mode
Similar to indirect register mode, but with
indirect auto increment mode,
The operand is incremented as part of the
instruction.
The format for operands is @Rn+.
This is useful for working on blocks of data.

Indirect auto increment

mode
Example 6: Move the contents of the source
address (contents of R4) to the destination
(register R5), then increment the value in
register R4 to point to the next word.
Before operation: R4=A002h R5=050Ah
Loc:0xA002=0123h
Operation: MOV @R4+, R5
After operation: R4= A004h R5=0123h
Loc:0xA002=0123h

Immediate mode
Immediate mode is used to assign
constant values to registers or
memory locations
Example 7: Move the immediate constant E2h
to the destination(register R5).
Before operation: R4=A002h R5=050Ah
Operation: MOV #E2h, R5
After operation: R4= A002h R5=00E2h

Absolute mode
Similar to Symbolic mode, with the
difference that the label is preceded by &.
Example 4: Move the content of source address XPT to the
destination address YPT.

Before operation: Location XPT=A002h

Location YPT=050Ah
Operation: MOV &XPT, &YPT
After operation: Location XPT= A002h
Location YPT=A002h

Clock Generator
These are the internal clocks, which
are the same in all devices:
Master clock, MCLK, is used by
the CPU and a few peripherals.
Subsystem master clock, SMCLK,
is distributed to peripherals.
Auxiliary clock, ACLK, is also
distributed to peripherals.

Contd..
ACLK comes from a low-frequency
crystal oscillator, typically at 32 KHz.
MCLK and SMCLK are supplied from
the DCO, which is controlled by a
frequency-locked loop (FLL). This
locks the frequency at 32 times the
ACLK frequency, which is close to
1MHz for the usual watch crystal.

Exceptions: Interrupts
and Resets
Interrupts: Usually generated by
hardware (although they can be
initiated by software)
Resets: Again usually generated by
hardware, either when power is applied
or when something catastrophic has
happened and normal operation cannot
continue. A reset causes the device to
(re)start from a well-defined state.

MSP430 Architecture

16-bit RISC CPU

Efficient, ultra-low power CPU
C-compiler friendly
RISC architecture
27 core instructions
24 emulated instructions
7 addressing modes
Constant generator
Single-cycle register operations
Memory-to-memory atomic
addressing
Bit, byte and word processing
20-bit addressing on MSP430X for
Flash >64KB

Flash memory
Most common type of memory
Practical difference between EPROM
and Flash is individual bites of
EPROM can be erased.
Flash can be erased only blocks.

ADC
ADC to processes quantities of the
real world.
Example sound , pressure ,force
Sensors / Actuators

Tools
Simulator
Emulator
JTAG

Software
What is the difference between
writing a program in desktop and
small micro controller
Machine code
Assembly Language
C Language