Professional Documents
Culture Documents
DSD
DSD
Design
Course Introduction
and
VHDL Fundamentals
(Lecture #1)
Course Introduction
Course Info
Course #: EE 09 505
Course Objective:
Textbooks
1. J. Bhasker,VHDL Primer, Prentice Hall India
2.John F Wakerly, Digital Design, Pearson
Education, Delhi, 2002
3.Morris Mano,Digital Design, Pearson
Education, Delhi, 2002
4. A Anandakumar, Digital
Electronics,Prentice Hall India Feb 2009.
(Module IV)
Discrete
Information
Processing
System
System State
5
Discrete
Outputs
State present
State updated at discrete times
=> Synchronous Sequential System
State updated at any time
=>Asynchronous Sequential System
State = Function (State, Input)
Output = Function (State, Input)
6
Count Up
Reset
0 0 1 3 5 64
Inputs:
Outputs:
Visual Display
State:
Module#1
Introduction to VHDL
Behavioral Simulation
Register Transfer
Level Design
RTL Simulation
Validation
Logic Design
Logic Simulation
Verification
Fault Simulation
Circuit Design
Timing Simulation
Circuit Analysis
Functional Design
Physical Design
VHDL Model
Functional Design
VHDL Model
Register Transfer
Level Design
Logic Simulation
Synthesis
Behavioral Simulation
(VHDL )
Timing Extraction
Introduction to VHDL
What is VHDL?
Fall 2010
11
A VHDL file
Entity
Architecture body
VHDL 1. ver.0a
12
VHDL Example
Library declaration
Entity declaration
library ieee;
use ieee.std_logic_1164.all;
entity XOR2 is
port
(A, B : in std_logic ;
Z
: out std_logic);
end XOR2;
Z <= A xor B;
end EXD;
Page 13
Entity Declaration
Name
Any legal VHDL identifier
Legal names
rs_clk
ab08B
A_1023
Illegal names
_rs_clk
signal#1
A__1023
rs_clk_
Port Mode
* The port mode of the interface describes the direction of the
data flow with respect to the component
* The five types of data flow are
- In
: data flows in this port and can only be read
(this is the default mode)
- Out
: data flows out this port and can only be written to
- Buffer : similar to Out, but it allows for internal feedback
- Inout
: data flow can be in either direction with any
number of sources allowed (implies a bus)
- Linkage: data flow direction is unknown
Sample PORT declaration syntax:
Type of Data
* The type of data flowing through the port must be specified to
complete the interface
* Data may be of many different types, depending on the
package and library used
* Some data types defined in the standards of IEEE are:
o Bit, Bit_vector
o Boolean
o Integer
o std_ulogic, std_logic
Architecture Declaration
Data Objects
There are three types of data objects:
Signals
Can be considered as wires in a schematic.
Can have current value and future values.
Constant Declaration
A constant can have a single value of a given type.
A constants value cannot be changed during the
simulation.
Constants declared at the start of an architecture
can be used anywhere in the architecture.
Constants declared in a process can only be used
inside the specific process.
CONSTANT constant_name : type_name [ : = value];
CONSTANT rise_fall_time : TIME : = 2 ns;
CONSTANT data_bus : INTEGER : = 16;
Variable Declaration
Variables are used for local storage of data.
Variables are generally not available to multiple
components or processes.
All variable assignments take place immediately.
Variables are more convenient than signals for
the storage of (temporary) data.
Signal Declaration
Signals are used for communication between
components.
Signals are declared outside the process.
Signals can be seen as real, physical signals.
Some delay must be incurred in a signal assignment.
Data Types
Types
Access
Composite
Subtype
Scalar
Integer
Real
Array
Enumerated
Physical
Record
Scalar Types
* Integer Types
- Minimum range for any implementation as defined
by standard: -2,147,483,647 to 2,147,483,647
Composite Types
* Array Types:
- Used to collect one or more elements of a similar type
in a single construct
- Elements can be any VHDL data type
Access Types
* Access
- Similar to pointers in other languages
- Allows for dynamic allocation of storage
- Useful for implementing queues, fifos, etc.
Subtypes
* Subtype
- Allows for user defined constraints on a data type
- May include entire range of base type
- Assignments that are out of the subtype range result
in an error
Summary
* VHDL has several different data types available to the
designer
* Enumerated types are user defined
* Physical types represent physical quantities
* Arrays contain a number of elements of the same type or
subtypes
* Records may contain a number of elements of different
types or subtypes
* Access types are basically pointers
* Subtypes are user defined restrictions on the base type
Subprograms
Similar to subprograms found in other languages
Allow repeatedly used code to be referenced
multiple times without rewriting
Break down large blocks of code into small, more
manageable parts
VHDL provides functions and procedures
Subprograms
(contd)
Functions
RETURN
RETURN BIT
BIT IS
IS
multiple
multiple values
values
FUNCTION
FUNCTION add_bits2
add_bits2 (a,
(a, bb :: IN
IN BIT)
BIT) RETURN
RETURN BIT
BIT IS
IS
VARIABLE
VARIABLE result
result :: BIT;
BIT; --- variable
variable is
is local
local to
to
function
function
BEGIN
BEGIN
result
result :=
:= (a
(a XOR
XOR b);
b);
RETURN
RETURN result;
result; --- the
the two
two functions
functions are
are equivalent
equivalent
END
END add_bits2;
add_bits2;
Functions
Functions
Procedures
May produce multiple output values
Are invoked by statements
May modify the parameters
PROCEDURE
PROCEDURE add_bits3
add_bits3 (SIGNAL
(SIGNAL a,
a,
SIGNAL
SIGNAL temp_result,
temp_result,
b,
b, en
en :: IN
IN
temp_carry
temp_carry
BIT;
BIT;
:: OUT
OUT BIT)
BIT) IS
IS
BEGIN
BEGIN --- procedures
procedures can
can return
return multiple
multiple values
values
temp_result
temp_result <=
<= (a
(a XOR
XOR b)
b) AND
AND en;
en;
temp_carry
temp_carry <=
<= aa AND
AND bb AND
AND en;
en;
END
END add_bits3;
add_bits3;
Procedures (cont)
Libraries
* Library is a place to which design units may be compiled.
*Two predefined libraries are the IEEE and WORK
libraries.
* IEEE standard library contains the IEEE standard design
units. (e.g. the packages: std_logic_1164, numeric_std).
* WORK is the default library.
* VHDL knows library only by logical name.
Libraries
How to use ?
library ieee;
* Design units within the library must also be made visible via
the use clause.
Packages
* Packages are used to make their constructs visible to other
design units.
Package
Package declaration
Package body
(optional)
Package Declaration
Example of a package declaration
package my_package is
type binary is (on, off);
constant pi : real : = 3.14;
procedure add_bits3 (signal a, b, en : in bit;
signal temp_result, temp_carry : out bit);
end my_package;
Package Body
* The package declaration contains only the declarations of
the various items
* The package body contains subprogram bodies and other
declarations not intended for use by other VHDL entities
Package
How to use ?
* A package is made visible using the use clause.
Modeling Styles
Behavioral Modeling
Explicit definition of mathematical
relationship between the input and
output
No implementation information
Structural Modeling
Implicit definition of I/O relationship
through particular structure
Interconnection of components