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Flattened Butterfly Topology For On-Chip Networks: John Kim, James Balfour, and William J. Dally Presented by Jun Pang
Flattened Butterfly Topology For On-Chip Networks: John Kim, James Balfour, and William J. Dally Presented by Jun Pang
High-radix networks
Goal: how does on-chip network use highradix routers to reduce latency & energy
On-chip network
Latency:
Topology
Fig. 3a
Switch architecture
Evaluation
Scalability
Concentrate factor
Dimension of the flattened butterfly
Hybrid approach
Flattened-butterfly:
interesting idea
Maximum distance between nodes=2
Non-minimal routing to balance load
Bypassing channel to reduce latency
Lower latency and power, high throughput compared to
mesh
Concerns: