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  • M.Jaseel Quest Global

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    RAMIZKHAN124
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    The document discusses static timing analysis (STA) concepts like clock skew, jitter, setup and hold timing checks, and STA procedures. It provides examples of calculating minimum clock period and input/output timing constraints accounting for register delays, logic delays, setup times, hold times, and clock skew. The key information is: 1. STA involves checking for setup and hold violations on all register-to-register paths and determining minimum clock period based on critical paths. 2. Skew and jitter impact the available time at synchronization points and can cause violations if not accounted for in timing analysis. 3. The minimum clock period is calculated based on the path with maximum delay through registers and logic plus setup

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    STA_DAY_1

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    The document discusses static timing analysis (STA) concepts like clock skew, jitter, setup and hold timing checks, and STA procedures. It provides examples of calculating minimum clock period and input/output timing constraints accounting for register delays, logic delays, setup times, hold times, and clock skew. The key information is: 1. STA involves checking for setup and hold violations on all register-to-register paths and determining minimum clock period based on critical paths. 2. Skew and jitter impact the available time at synchronization points and can cause violations if not accounted for in timing analysis. 3. The minimum clock period is calculated based on the path with maximum delay through registers and logic plus setup

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pptx, pdf, or txt
    52 views25 pages

    M.Jaseel Quest Global

    Uploaded by

    RAMIZKHAN124
    The document discusses static timing analysis (STA) concepts like clock skew, jitter, setup and hold timing checks, and STA procedures. It provides examples of calculating minimum clock period and input/output timing constraints accounting for register delays, logic delays, setup times, hold times, and clock skew. The key information is: 1. STA involves checking for setup and hold violations on all register-to-register paths and determining minimum clock period based on critical paths. 2. Skew and jitter impact the available time at synchronization points and can cause violations if not accounted for in timing analysis. 3. The minimum clock period is calculated based on the path with maximum delay through registers and logic plus setup

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pptx, pdf, or txt
    of 25

    Mohammed Jaseel

    STA

    M.Jaseel

    QuEST Global

    CLASSICAL PROBLEM IN STA


    Delay through the register (tclk-q) =0.6ns
    Set-up time tsu = 0.4ns
    What is the minimum clock period?

    Mohammed Jaseel

    Tclk 0.6 ns + 8 ns + 0.4 ns

    Tclk tclk-q (register) + tpd logic (longest) + tsu (destination register)

    SKEW

    Mohammed Jaseel

    Skew is the difference in timing between


    two or more signals, maybe data, clock or
    both.

    Skew = 20ns-5ns = 15ns

    STA SKEW EXAMPLE


    setup time for 1.5
    Maximum clock skew is .5 ns

    Mohammed Jaseel

    1.5+3+1.5+0.5=6.5 ns

    POSITIVE CLOCK SKEW

    Clock and data flow in the same direction

    T + |del| >= tc-q+ tplogic + tsu


    T >=tc-q+ tplogic + tsu - |del|
    thold+ |del| tcdlogic+ tcdreg
    thold tcdlogic+ tcdreg |del|

    Mohammed Jaseel

    Del > 0:
    Improves
    performance,
    but makes
    thold harder
    to meet

    NEGATIVE CLOCK SKEW

    T - |del| >= tc-q+ tplogic + tsu


    T >=tc-q+ tplogic + tsu +|del|
    thold-| del| tcdlogic+ tcdreg
    thold tcdlogic+ tcdreg +|del|

    Mohammed Jaseel

    Del < 0:
    degrade
    performance,
    but makes
    thold easier
    to meet

    CLOCK JITTER

    Mohammed Jaseel

    Clock jitter can be defined as deviation of a clock


    edge from its ideal location.

    SOURCES OF CLOCK SKEW AND


    JITTER IN CLOCK NETWORK

    Mohammed Jaseel

    CLOCK JITTER ANALYSIS IN SYNC


    CKTS

    Mohammed Jaseel

    T -2tjitter>=tc-q+ tplogic + tsu


    T >=tc-q+ tplogic + tsu + 2tjitter

    EFFECT OF JITTER
    Jitter affects the clock delay
    The time the clock is available at sync points,
    setup and hold of the path elements are affected
    by it
    Setup hold or setup violations

    Mohammed Jaseel

    10

    COMBINED IMPACT OF SKEW AND


    JITTER

    Mohammed Jaseel

    T >= tc-q+ tplogic + tsu -del+ 2tjitter


    thold tcdlogic+ tcdreg del2tjitter

    11

    MIN MAX PATH

    Mohammed Jaseel

    12

    PATHS
    Timing paths can be divided as per the type of signals (e.g clock signal,
    data signal etc).
    Mohammed Jaseel

    13

    FEW MORE PATHS


    Critical Path
    False Path

    Mohammed Jaseel

    14

    PATHS CONTD..
    Multicycle path
    Single Cycle Path
    Launch Path and Capture Path

    Mohammed Jaseel

    15

    SETUP TIMING CHECK

    Mohammed Jaseel

    16

    SETUP TIMING CHECK EXAMPLE

    Mohammed Jaseel

    17

    Tlaunch + Tck2q + Tdp +Tsetup < Tcapture + Tcycle

    HOLD TIMING CHECK

    Mohammed Jaseel

    18

    HOLD CHECK EXAMPLE

    Mohammed Jaseel

    19

    Tlaunch + Tck2q + Tdp > Tcapture + Thold

    SETUP-HOLD ANALYSIS WITH SKEW

    Mohammed Jaseel

    T + |del| >= tc-q+ tplogic + tsu


    T >=tc-q+ tplogic + tsu - |del|

    T - |del| >= tc-q+ tplogic + tsu


    T >=tc-q+ tplogic + tsu +|del|

    thold+ |del| tcdlogic+ tcdreg


    thold tcdlogic+ tcdreg |del|

    thold-| del| tcdlogic+ tcdreg


    thold tcdlogic+ tcdreg +|del|

    tcdlogic -> min combo delay

    tcdreg -> min reg delay

    20

    STA PROCEDURE STEP 1


    Check for internal hold time violations
    for every ff-to-ff path, check
    (minimum ff prop. delay) + (minimum comb.
    circuit delay) (hold time) + (clock skew)
    fix violations by adding delay
    no violations possible if
    hold-time<(min-ff-prop-delay)skew

    Mohammed Jaseel

    21

    STA PROCEDURE STEP 2


    Determine minimum clock period
    find ff-to-ff path with largest value of
    (maximum ff prop. delay) + (maximum comb.
    circuit delay)+ (setup time) + (clock skew)

    Mohammed Jaseel

    22

    STA PROCEDURE STEP 3


    Input timing analysis
    each input must be stable from
    (clock_edge) - ((maximum input-to-ff delay) +
    (setup time))
    to
    ((clock_edge) + (hold time)) - (minimum input-toff delay)

    Mohammed Jaseel

    23

    STA PROCEDURE STEP 4


    Timing analysis for synchronous outputs
    synchronous outputs have potential to change
    any time from
    (clock_edge) + (minimum clock-to-output
    delay)
    to
    (clock_edge) + (maximum clock-to-output
    delay)

    Mohammed Jaseel

    24

    STA EXAMPLE
    flop setup time is 2 ns, hold time is 0.5 ns ,
    flop delay is between 1 and 3 ns.
    What
    isthe
    thesmallest
    latest time
    relative
    What is
    clock
    periodtofor
    clock skew is 0.3 ns.
    What
    Is
    this
    iscircuit
    the latest
    subject
    timeto
    after
    internal
    the
    the
    which the circuit is not subject to

    Mohammed Jaseel

    clock
    hold
    when
    output
    X can
    be
    clock,
    whenviolations?
    it is safe
    for input
    B to
    setup time
    changing?
    time
    violations?
    change?

    25

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