Real Time Audio Signal Processing System

SPIRNG 2016
520: SYSTEM ON CHIP DESIGN

ByRadhika Sontakay
Sagar Kanphade
California State University Northridge

Table of content

Objectives
Abstract
Block Diagram
Design Flow
Hardware Platform
Hardware Implementation
Source Code

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Objectives

Explore the digital and analog components needed to process

an analog signal such as audio.
Study the architecture of the ADAU1761 audio Codec.
Study the Inter-Integrated Circuit (I2C) interface protocol and
use it to communicate with an external chip.
Study the Inter-IC Sound (I2S) interface protocol and utilize it
to exchange audio data with an external chip.
Build a simple digital audio processing application.

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Digital Audio Processing System

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Abstract

Audio digital signal processing is the intentional modification of the digital

signals. With this processing method we can store, compress , transmit and
enhance any digital signal.
The aim of this project is to utilize two analog to digital converters of the
ADAU1761 audio Codec chip to sample stereo audio (right channel + left
channel) at 48 KHz.
The digitized samples are sent to the Zynq chip through the I2S standard
audio bus for processing.
On the Zynq chip, a dedicated hardware called NCO (Numerically
Controlled Oscillator) is responsible for generating samples of sine wave at
selected frequencies. These samples of sine wave are superpositioned on
the received audio samples.
The modified audio samples (received audio samples + sine wave samples)
are sent over the I2S bus to the DAC converters of the Codec for playing on
a speaker ( or an earphone) connected to the line out port of the chip.
Communication to codec is done by I2C bus on the PS of Zynq chip.

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Block Diagram

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Design Flow

STEP 1
Create a
Vivado
project

STEP 2
Add and
configure
processing
system(I2C
bus)

Write a C App and

verify
functionality
STEP 7
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STEP 3
Add I2S
audio
controller
and NCO IPs
to repository

Generate
bitstream and
export to
SDK
STEP 6

STEP 4
Connect I2S
and NCO IPs
to processing
system

Add Dual
channels
GPIO
STEP 5
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Hardware Platform

ZEDBOARD Development Kit

Zynq 7000 SoC
ADAU1761 Codec
I2C Bus
I2S Bus
Numerically Controlled Oscillator
Dual-core ARM Cortex A9
Onboard USB-JTAG Programming
USB UART
User Inputs
Slide switches

3.5mm jack male-to-male-stereo cable

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ADAU1761 Codec
This is a chip equipped with two 24-bit ADCs and two 24-bit DACs with a
wide range of supported sampling rate from 8Khz to 96Khz.
For audio processing and mounted on board through I2C bus.
The sampling frequency is generated by the PLL logic which is driven by a
master clock supplied by an external source.

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ADAU1761 Codec Ports

CODEC has two ports
1. Data port
Captured and transmitted digital audio is read/written through the
data port of the chip, the data port is compliant with the I2S audio
interface standard.
2. Control port
The control port essentially provides access to the chips control
registers.
There are 67 control registers; the addresses of these 67
registers are in the range of 0x4000 to 0x40FA.
These registers can perform the following function:
Controlling the internal audio amplifiers gain.
Enabling/disabling mixers.
Switching ON/OFF various parts of the chip.
Setting up the sampling frequency.
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I2C bus
Used to configure the Audio chip by writing to its
control registers.
The ADAU1761 Codec is always a slave on the bus,
which means that it cannot initiate a data transfer.
The serial data (SDA) line on the I2C bus carry
configuration commands between the I2C master
controller (Zynq chip) and the Codec which is synced
by serial clock (SCL) line.
I2C slave devices are recognized by a unique 7-bits
address.

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I2C bus write operation

In order to write a byte to a control register using I2C , four bytes
were actually sent:

Byte1: I2C address for the ADAU1761 (0x38).

Byte2: Sub-address high byte of the control register.
Byte3: Sub-address low byte of the control register.
Byte4: The data byte to be written in the control register.
register

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I2S BUS
The I2S (Inter-IC Sound) is a de-facto standard for
transferring audio data within digital systems.
I2S protocol have two clocks and data lines known as the
serial audio data in/out lines:
1. The Left-Right clock (LRCLK).
2. Bit clock (BCLK).
3. Serial audio data in/out lines (SDATA_ADC) and
(SDATA_DAC).

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I2S protocol

The function of the Left-Right clock (LRCLK) is to identify the audio system
sample rate and frame the two channels of audio data that exist on the single
audio data line.
The Bit clock (BCLK) is a serial clock that is used to shift the time of audio
data bits into or out of the data audio port.
Serial audio data in/out (SDATA) lines carry the audio data, whether it is
coming out of the ADC, or sent to the DAC.

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Numerically Controlled Oscillator

The NCO is used to generate a sine wave at a desired
frequency (within the audible range), the NCO is implanted in
hardware as an AXI core to provide accurate timing.
Two driver functions are used in this project:
1. XNco_SetStep_size_v(): Used to setup the frequency of the
sine wave.
2. XNco_GetSine_sample_v(): Used to get the sine wave
sample at the requested frequency.

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Flow chart

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Northridge

Hardware Configurations
Two IPs are used:
1.zed_audio_ctrl IP controller responsible for exchanging data
with the ADAU1761 Codec through the I2S protocol.
2.xilinx_com_hls_nco_1_0 IP controller responsible
for generating sine waves at a desired frequency.
I2C1,USB0,ENET0,SD0, UART1 are enabled on the MIO
configuration.
FCLK1 is set to 10 MHz and its made external.
GPIO is configured to have two channels, one for LEDs and
one for switches instead of using two separate GPIOs.

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Software Configurations
Constraint file is used to connect the block diagram design
pins like
BCLK, LRCLK, SDATA_O, SDATA_I, FCLK_CLK1, iic_1_scl
_io, iic_1_sda_io, ADDRESS[0], and ADDRESS[1] ports to
the actual physical pins connected to the ADAU1761 audio
Codec.
Source and header files are used so that its BSP are
compiled automatically and the executable .elf file is
generated.
This is the executable file that the ARM processor on the PS
side of the Zynq will execute.
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Hardware Implementation

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Constraint file

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Source Code

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Overview

I2C bus
Analog signals
using two ADCs
at 48KHz

Superimposed
Zynq chip
signal(sine
wave +
Digitalized
Sine wave input audio
sample
zed_audio_ctrl
IP used
I2S bus

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NCO

Speaker/
Headphones

Output

Demo Video

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