MECA587 Advanced

Digital Design for

Mechatronics
The origin of Moores Law
... and its consequences

Faik Baskaya, Boazii University

We came a very long way to enjoy

the benefits of electronics technology

 Calculus (from Latin calculus meaning

pebble, plural calculi) in its most general
sense is any method or system of
3
calculation. [Wikipedia]

The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
4

ENIAC - The first electronic computer (1946)

The Transistor Revolution

First transistor
Bell Labs, 1948

Bipolar junction transistor (BJT)

VBE
VT

I c I B I Se

The First Integrated Circuits

Bipolar logic
1960s

ECL 3-input Gate

Motorola 1966

The MOS Miracle

We needed a substrate for our chip. So we looked at the
substrate of the earth itself. It was mostly sand. So we used
that. We needed a metal conductor for the wires and switches
on the chip. We looked at all the metals in the earth and found
aluminum was the most abundant. So we used that. We
needed an insulator and substances both to protect the chip
chemically during manufacture and to insulate it electrically in
use. We saw that silicon in sand mixed with oxygen in the air to
form silicon dioxide a kind of glass. The perfect insulator to
protect the chip. So we used that.
-- Gordon Moore
9

Courtesy, D. Foty

Metaloxidesemiconductor fieldeffect transistor (MOSFET)

10

N-type and P-type MOS on the

same chip: Complementary
MOS (CMOS)
NFET

11

PFET

Moores Law
In 1965, Gordon Moore noted that
the number of transistors on a chip
doubled every 18 to 24 months.
He made a prediction that
semiconductor technology will
double its effectiveness every 18
months

12

L O G2 O F T H E N U M B E R O F
C O M P O N E N T S P E R IN T E G R A T E D F U N C TIO N

13

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

195 9
1960
1961
1962
1963
1964
1965
1966
196 7
1968
196 9
1970
1971
1972
1973
1974
1975

Moores Law

Electronics, April 19, 1965.

 and it turns out as:

Gordon Moore, co-founder of Intel predicted this trend in 1965.

Road-Map
Year 2004 90nm
2007 65 nm
2010 45nm
2013 32 nm
2016 22 nm

http://www.intel.com/technology/silicon/mooreslaw/

Enough data storage capacity for 5-10 years continuous

audio/video recording of life experience

Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

15

Intel Pentium (IV) microprocessor

2000
42 million transistors
2 GHz operation

16

Evolution in Complexity

17

A self-fulfilling prophecy?
Gordon Moore was the co-founder of
Intel, so his predictions are more
likely to be turned into reality than
ours.
The whole company tried to keep-up
with this expectation.
Competitors also had to keep-up with
Intel.

18

Moores law in
Microprocessors
Transistors (MT)

1000

2X growth in 1.96 years!

100
10

486

1
386
286

0.1
0.01

P6
Pentium proc

8086
8080
8008
4004

8085

0.001
1970

1980

1990
Year

2000

2010

Transistors
Transistors on Lead Microprocessors double every 2 years
19

Courtesy, Intel

Die Size Growth

Die size (mm)

100

10
8080
8008
4004
1
1970

8086
8085

1980

286

386

P6
Pentium
proc
486

~7% growth per year

~2X growth in 10 years

1990
Year

2000

2010

Die
Die size
size grows
grows by
by 14%
14% to satisfy Moores Law
20

Courtesy, Intel

Frequency
Frequency (Mhz)

10000
Doubles every
2 years

1000
100
10

8085

1
0.1
1970

8086 286

386

486

P6
Pentium proc

8080
8008
4004
1980

1990
Year

2000

2010

Lead
Lead Microprocessors
Microprocessors frequency
frequency doubles
doubles every
every 22 years
years
21

Courtesy, Intel

Power Dissipation
Power (Watts)

100
P6
Pentium proc
10
8086 286
1

8008
4004

486
386

8085
8080

0.1
1971

1974

1978

1985

1992

2000

Year

Lead
Lead Microprocessors
Microprocessors power continues to increase
22

Courtesy, Intel

Power will be a major

problem
100000

18KW
5KW
1.5KW
500W

Power (Watts)

10000
1000
100

Pentium proc

286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power
Power delivery and dissipation
dissipation will
will be
be prohibitive
prohibitive
23

Courtesy, Intel

Power density
Power Density (W/cm2)

10000

Rocket
Nozzle

1000

Sun
Surface

Nuclear
Reactor

100

8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970

1980

1990
Year

2000

2010

Power
Power density
density too
too high to keep junctions at low temp!
temp!
24

Courtesy, Intel

A Modern CMOS Process

gate-oxide
TiSi2

AlCu
SiO2

Tungsten
poly
p-well

n+

p-epi

p+
p+

Dual-Well Trench-Isolated CMOS Process

25

SiO2

n-well

Manufacturing The IC: PhotoLithographic Process

optical
mask
oxidation

photoresist
removal (ashing)

photoresist coating
stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step

26

spin, rinse, dry

Patterning of SiO2
Chemical or plasma
etch
Si-substrate

Hardened resist
SiO
2

(a) Silicon base material

Si-substrate

Photoresist
SiO
2
Si-substrate

(d) After development and etching of resist,

chemical or plasma etch of SiO
2
Hardened resist
SiO
2

(b) After oxidation and deposition

of negative photoresist
UV-light
Patterned
optical mask

Si-substrate
(e) After etching

Exposed resist
Si-substrate
(c) Stepper exposure

27

SiO
2
Si-substrate
(f) Final result after removal of resist

Design Metrics
How to evaluate performance of a
digital circuit (gate, block, )?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function

28

Cost of Integrated Circuits

NRE (non-recurrent engineering)
costs
design time and effort, mask generation
one-time cost factor

Recurrent costs
silicon processing, packaging, testing
proportional to volume
proportional to chip area
29

NRE Cost is Increasing

30

Die Cost
Single die

Wafer
Going up to 12 (30cm)
31

From http://www.amd.com

Cost per Transistor

cost:

-per-transistor

1
0.1

Fabrication capital cost per transistor (Moores law)

0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982

1985

1988

1991

1994

1997

2000

2003

2006

2009

A transistor is the cheapest product made by humankind!

32

2012

The four reasons of CMOS success

1.
2.
3.
4.

Conductivity can be controlled at will.

Dual conductivity (negative and positive).
Ability to grow in-situ oxide on silicon.
CMOS amenability to scaling.

. Note: The first three are material

First and second are general, third is silicon-only

. While the fourth is intellectual (CMOS

only)
33

Courtesy, D. Foty

Challenges in Digital Design

DSM

1/DSM
Macroscopic Issues
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.

Microscopic Problems
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.
Everything Looks a Little Different

34

and Theres a Lot of Them!

Design crisis
Process technology provides a 59% per year increase of
complexity (Moores law)
Design efficiency increases by only 25% per year
Log #
transistors

Technology
59% / year
Design
gap
Design
25% / year

Time
35

Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x
more functions per chip; chip cost does not
increase significantly
Cost of a function decreases by 2x
But
How to design chips with more and more
functions?
Design engineering population does not double
every two years

Hence, a need for more efficient design

methods
36

Exploit different levels of abstraction

Design crisis revisited

The design gap has been predicted for the last two
decades
Yet, in every new technology, we design chips of 1 cm 2
that are completely utilized
Technology
59% / year
average

Log #
transistors

New
process
New reuse
technology
method

Design
25% / year &
paradigm
shifts

Time
37

Consequences for design

IC design needs to handle

Integrated systems (SoC)

Increasing complexity
Fast time to market (too late = no business)
Hardware and software
High processing speed and / or low power

This requires a design process that is

Predictable in time and performance
Efficient

The key elements of such a design process are

High level of re-use
Silicon prototyping

38

Intellectual Property

A Protocol Processor for Wireless

Designing each macromodule can be very expensive and time

consuming. Instead, a system can be constructed by purchasing
designed modules from third parties and use them as they are.
Examples of commonly available modules: DSP processors, embedded
microcontrollers, bus interfaces (PCI), MPEG coding, decoding, etc.
39

Adapted from (Jan. Rabaey, Digital Integrated Circuits). Copyright 2003 Prentice Hall/Pearson

How to design very large

circuits?
As the complexity grows, more design
effort is required.
Putting more and more engineers to work
on the project is not a good solution
increases costs
prone to human errors

Divide and conquer is the only way to go

Hierarchical approach must be used to design
very large circuits.
40

Design Abstraction Levels

SYSTEM

MODULE
+
GATE

CIRCUIT

DEVICE
G
S
n+

41

D
n+

Different views of the same

design Layout view
Logic (gate) view

Circuit (transistor) view

VDD

VDD
M2
Vout

Vin

M1
42

M4
Vout2

M3
42

Gajkskis Y chart

43

Gajkskis Y chart

44

VLSI Design Cycle

45

Physical Design Cycle

Circuit
Design

Partitioning

Floorplanning
&
Placement

Routing

Compaction

46

Fabrication

Classifications of Integrated Circuits

Microprocessors
Memory chips (SRAM, DRAM, Flash, ROM, PROM)
Standard Components (74LS..)
Application-Specific Integrated Circuits
Widely used in communication, network, and multimedia systems
For a given application, ASIC solutions are normally more
effective than the solutions based on running software on
microprocessors (HARDWARE ACCELERATION!)
Many chips in cellular phones, network routers, and game consoles
are ASICs
Most SoC (Systems-on-a-Chip) are ASICs
47

Impact of Implementation Choices

48

There is a trade-off between a custom design and a programmable design.

Programmable design can be reconfigured to debug problems or to change
functionality. However, it has a very low energy efficiency (the number of
operations that can be performed for a given amount of energy).

ASIC Design Methodologies

ASIC Design Methodology

Full custom
design
This approach is
extremely slow,
expensive
Only used to
design very high
performance
systems

Standard cell
based design
This approach is
reasonably fast,
less expensive
Most ASICs are
currently designed
using this method

Gate array
based design

FPGA based
design

This approach is
fast and less
expensive

Very fast and

cost-effective
design process

Relatively slow
performance

Slow performance

Choice depends on area, speed, power dissipation, design time and cost.
49

Full Custom Design Methodology

Function Partition
Layout Design
Including placement & routing
Schematic Design
Including transistor sizing
Fail

Fail

Function
And Timing
verification

Post-Layout
simulation
Pass
Go to fabrication

Pass
ASIC Chips
It is a time consuming all manual process, pre-developed libraries not needed.
50

Full Custom Design Methodology

Design a chip from scratch.
Engineers design some or all of the logic cells, circuits,
and the chip layout specifically for a full-custom IC.
Custom mask layers are created in order to fabricate
a full-custom IC.
Advantages: complete flexibility, high degree of
optimization in performance and area.
Disadvantages: large amount of design effort, expensive.

51

Standard Cell Based Design Methodology

High-level (RTL or behavioral-level) design
Fail

High-level verification

VHDL or Verilog coding

VHDL or Verilog simulation

Pass
Logic gate library

Logic synthesis
Fail

Gate-level verification
Pass
Cell layout library

Placement & Routing

Fail

52

Post-Layout verification

Pass

Go to fabrication

It is highly automated, but needs pre-developed libraries.

Standard Cell Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

Adapted from (Jan. Rabaey, Digital Integrated Circuits). Copyright 2003 Prentice Hall/Pearson
53

Standard Cell Based Design Methodology

Use pre-developed logic cells from standard-cell library as
building blocks.
As full-custom design, all mask layers need to be customized to
fabricate a new chip.
Advantages: save design time and money, reduce risk
compared to full-custom design.
Disadvantages: still incurs high non-recurring-engineering
(NRE) cost and long manufacture time.
Library Cells
D
B
Chip layout
54

A
D

Gate Array Based Design Methodology

Generating schematic (netlist)

The netlist can be designed

using full-custom or
standard-cell based
design method

Placement & Routing

Cell layout library

Post-Layout verification

Make the final connections for the

pre-fabricated gate array base
Pre-fabricated gate array template
(contains unconnected transistors) ASIC Chips

55

This approach is faster and cheaper than using standard-cell, because part of
the fabrication process has been complete.

Gate Array Based Design Methodology

Parts of the chip (transistors) are pre-fabricated, and other parts
(wires) are custom fabricated for a particular customers circuit.

Gate Array

Sea-of-Gates

Advantages: cost saving (fabrication cost of a large number of

identical template wafers is amortized over different
customers), shorter manufacture lead time.
Disadvantages: performance not as good as full-custom or
standard-cell-based ICs.
56

FPGA-based Design Methodology

HDL coding &
Logic Synthesis

Schematic
Capture
netlist
FPGA cell
library

Implementation
Fail
Verification
Pass

Technology mapping
Placement & routing
Timing verification
Download

Generate FPGA Bit Stream

FPGA
This approach has extremely fast turn-out time since FPGA devices have already
been fabricated.
57

Comparison of Design Methodologies

Full custom
design

Standard cell
based design

Gate array
based design

FPGA-based
design

+++

++

+++

++

--

++

++

---

--

+++

All

All

Some

None

Fabrication time

---

--

+++

Time to Market

---

--

++

+++

Risk reduction

---

--

+++

Future design
modification

---

--

+++

Speed
Integration
density
High-volume
device cost
low-volume
device cost
Custom mask
layer

58

+ desirable; - not desirable