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A Scalable Approximate DCT Architecture For Efficient Hevc Compliant Video Coding
A Scalable Approximate DCT Architecture For Efficient Hevc Compliant Video Coding
ARCHITECTURE FOR
EFFICIENT HEVC COMPLIANT VIDEO
CODING
ABSTRACT
There are two reasons to consider the DCT of length 4 as the basic
module. Firstly, it allows computing DCTs of length 4, 8, 16, and 32
prescribed by HEVC.
Cont,.
Moreover, the DCTs generated by 4-point DCT not only involve lower
complexity but also offer better compression performance.
Full-parallel
and
area-constrained
architectures
for
the
proposed
approximate DCT are proposed to have flexible trade-off between area and
time complexities.
Cont,.
Using the same reconfiguration scheme 32-point DCT could be configured
for parallel computation of two 16-point DCTs or four 8-point DCTs or eight
4-point DCTs.
The proposed approach can be Implemented using Verilog HDL and
Simulated by Modelsim 6.4 c.
Finally its Synthesized by Xilinx tool and Implemented in FPGA Spartan 3
XC3S 200 TQ-144.
EXISTING SYSTEM
Cont,
More Complexity
PROPOSED SYSTEM
A 4x4 approximate DCT matrix is proposed, and then used that for generating all
higher length DCTs.
Firstly, it allows to compute DCTs of all the lengths 4, 8, 16, and 32 prescribed by
HEVC.
Moreover, the DCTs generated by 4-point approximate DCT not only involve lower
computational complexity but also offer better compression performance.
Provides better compressed image quality than the other approximate DCT
Increase in bit-rate
SOFTWARE REQUIREMENT
ModelSim6.4c
Xilinx 9.1/13.2
IMPLEMENTATION LANGUAGE:
Verilog HDL
HARDWARE REQUIREMENT
FUTURE ENHANCEMENT
We will reduce the Area with the help of Changing the Transpose Memory
ALTERNATE TITLES:
Title 1: An Efficient VLSI Implementation of scalable approximate DCT
architecture
Title 2: Design scalable approximate DCT architecture for Video Coding
Application
Title 3: FPGA Implementation of scalable approximate Discrete Cosine Transform
architecture