Design Rules

Jan M. Rabaey

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Cross-Section of CMOS Technology

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Design Rules

Interface between designer and process

engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

CMOS Process Layers

Layer

Color

Well (p,n)

Yellow

Active Area (n+,p+)

Green

Select (p+,n+)

Green

Polysilicon

Red

Metal1

Blue

Metal2

Magenta

Contact To Poly

Black

Contact To Diffusion

Black

Via

Black

Digital Integrated Circuits

Design Rules

Representation

Prentice Hall 1995

Intra-Layer Design Rules

SamePotential
Well
10

0
or
6

DifferentPotential
2

9
Polysilicon
2

Active
3

Metal1
Contact
orVia
Hole

2
2

Select

3
4

Metal2
3

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Transistor

Transistor Layout

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Vias and Contacts

2
4

Via
1

Metalto
1
ActiveContact

1
Metalto
PolyContact
3

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Select Layer
2
3

Select
2

1
3

Well

Substrate
Digital Integrated Circuits

Design Rules

Prentice Hall 1995

CMOS Inverter Layout

In

GND

VD D

Out
(a)Layout

A
n

psubstrate
n

Field
Oxide

(b)CrossSectionalongAA
Digital Integrated Circuits

Design Rules

Prentice Hall 1995