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MCBSD 14.7.2016 New
MCBSD 14.7.2016 New
MCBSD 14.7.2016 New
MICROCONTROLLER
BASED SYSTEM DESIGN
BE-EEE 07 SEMESTER
Collected by
C.GOKUL
AP/EEE
Velalar College of Engg & Tech,Erode
Syllabus
EE6008 MICROCONTROLLER BASED SYSTEM
DESIGN
UNIT-1
INTRODUCTION TO PIC
MICROCONTROLLER
UNIT-1 Syllabus
INTRODUCTION TO PIC MICROCONTROLLER
Introduction to
PIC
Microcontroller
What is PIC?
The term PIC or Peripheral Interface Controller,
has been coined by Microchip Technology Inc.
Low-end range, mid-range and high end range of
controllers.
CPU
(&
Data)
Memory
(Data)
CPU
12
14
16
(Program
)
Von Neumann
Architecture:
Harvard Architecture:
101 ASP
10
CISC
Traditionally, CPUs are CISC
Complex Instruction Set Computer (CISC)
Used in: 80X86, 8051, 68HC11, etc.
Many instructions (usually > 100)
Many, many addressing modes
Usually takes more than 1 internal clock cycle
(T cycle) to execute
Example:
MC68HC05:
0x55
LDAA
1000
1100
01010101
2 bytes, 2 cycles
RISC
PICs and most Harvard chips are RISC
Reduced Instruction Set Computer (RISC)
Used in: SPARC, ALPHA, Atmel AVR, etc.
Few instructions (usually < 50)
Only a few addressing modes
Executes 1 instruction in 1 internal clock cycle
(Tcyc)
Example:
PIC16CXXX:
MOVLW 0x55
1100XX 01010101
1 word, 1 cycle
PIC Microcontrollers
with
basic
I/O
applications
requiring
simple
interface
functions and small program & data memories
12C5XX
16C5X
16C505
Popularity of the
PIC microcontrollers
Speed:
Harvard
Architecture,
RISC
architecture, 1 instruction cycle = 4 clock
cycles
Instruction set simplicity: 35 instructions
Power-on-reset and brown-out reset
A watch dog timer (user programmable)
Four optional clock sources
Low power crystal, Mid range crystal, High
range crystal, RC oscillator (low cost)
Popularity of the
PIC microcontrollers
Programmable timers and on-chip ADC
Up to 12 independent interrupt sources
Powerful output pin control (25 mA (max.)
current sourcing capability per pin.)
EPROM/OTP/ROM/Flash memory option
I/O port expansion capability
Free assembler and simulator support from
Microchip at www.microchip.com
CPU Architecture
Harvard Architecture
instruction fetch & operation on data/accessing
of variables simultaneously
Specifications
Popular PIC microcontrollers
Special purpose register file (similar to SFR
in 8051).
Architecture of PIC16C74A
PC=13 bit
PM=14 - bit word
Program Memory
capacity
= 8k x 14 bit
Each instruction
of PIC 16C74A is
14 - bit long.
CPU registers
W, the working register
STATUS Register
C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode
FSR Register
(File Selection Register, address = 04H, 84H)
- 8-bit register - data memory address pointer
- indirect addressing mode.
CPU registers
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register.
- Accessing INDF access is the location pointed to
by FSR in indirect addressing mode.
PCL Register
(Program Counter Low Byte, address = 02H,
82H)
- lower 8-bits of the 13-bit program counter.
- both readable and writable register.
CPU registers
PCLATH Register
(Program Counter Latch, address = 0AH, 8AH)
Pipelinin
g
Register
File
Structure
Register File
Map
Orthogonal Instruction
Set: ALL instructions
can operate on ANY
data memory location
08h
09h
Data Bus
Bus
Data
07h
ALU
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
W
W
Decoded Instruction
from Program Memory:
Opcode
Opcode d
d
Arithmetic/Logic Function
to be Performed
Result
Destination
Address
Address
Address of Second Source
Operand
101 ASP
Slide
36
Instructio
n Setoverview
101 ASP
Slide
38
101 ASP
Slide
39
101 ASP
Slide
40
Byte
Byte Oriented
Oriented Operations
Operations
f,d
f,d Add
Add W
W and
and ff
f,d
f,d
clrf
clrf ff
clrw
clrw -comf
comf f,d
f,d
decf
decf f,d
f,d
decfsz
decfsz
incf
incf f,d
f,d
incfsz
incfsz
rlf
rlf
rrf
rrf
xorwf
xorwf f,d
f,d
Bit
Bit Set
Set ff
Bit
Bit Test
Test f,f, Skip
Skip ifif Clear
Clear
Clear
Clear W
W
Complement
Complement ff
f,d
f,d
Decrement
Decrement ff
Decrement
Decrement f,f, Skip
Skip ifif 00
addlw
addlw
andlw
andlw
f,d
f,d
Increment
Increment ff
Increment
Increment f,f, Skip
Skip ifif 00
call
call kk
clrwdt
clrwdt
Inclusive
Inclusive OR
OR W
W with
with ff
Move
Move ff
goto
goto
iorlw
iorlw
Move
Move W
W to
to ff
No
No Operation
Operation
movlw
movlw
retfie
retfie --
Rotate
Rotate Left
Left ff through
through Carry
Carry
Rotate
Rotate Right
Right ff through
through Carry
Carry
retlw
retlw kk
return
return
Subtract
Subtract W
W from
from ff
Swap
Swap nibbles
nibbles in
in ff
sleep
sleep -sublwk
sublwk
Go
Go into
into standby
standby mode
mode
Subtract
Subtract W
W from
from literal
literal
Exclusive
Exclusive OR
OR W
W with
with ff
xorlw
xorlw kk
Exclusive
Exclusive OR
OR literal
literal with
with W
W
ff
f,d
f,d
f,d
f,d
subwf
subwf
swapf
swapf
f,b
f,b
f,b
f,b
btfsc
btfsc f,b
f,b
btfss
Bit
btfss f,b
f,b
Bit Test
Test f,f, Skip
Skip ifif Set
Set
Literal
Literal and
and Control
Control Operations
Operations
iorwf
iorwf f,d
f,d
movf
movf f,d
f,d
movwf
movwf
nop
nop --
AND
AND W
W with
with ff
Clear
Clear ff
bcf
bcf
bsf
bsf
Bit
Bit Oriented
Oriented Operations
Operations
Bit
Bit Clear
Clear ff
f,d
f,d
f,d
f,d
101 ASP
kk
kk
Add
Add literal
literal and
and W
W
AND
AND literal
literal with
with W
W
--
Call
Call subroutine
subroutine
Clear
Clear Watchdog
Watchdog Timer
Timer
kk
kk
Go
Go to
to address
address
Inclusive
Inclusive OR
OR literal
literal with
with W
W
kk
--
Move
Move literal
literal to
to W
W
Return
Return from
from interrupt
interrupt
Return
Return with
with literal
literal in
in W
W
Return
Return from
from Subroutine
Subroutine
Slide
41
ADDLW
Hex
Dec
Data
Bus
ALU
FF
FF
FF
FF
FF
W
Register
Register File
FF
FF
FF
18
FF
FF
Bin
Execute
101 ASP
Reset
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
STATUS
2 1 0
1 0 0
Z DC C
Slide
42
PIC Microcontroller
Instruction Set
Outline
Instruction
set
Instruction description
Assembler directives
Instruction Set
PIC16Cxx
@
PIC16Fxx: 14bit word
(opcode)
Byte-oriented,
bit-oriented &
literal and
control
Instruction Set
cont
Instruction
Descriptions
ADDLW K
Add
ADDLW K
Instruction: ADDLW
cont
15H
Before
After
W = 10H
W = 25H
ADDWF f, d
Add
ADDWF f, d
Instruction: MOVLW
17H
ADDWF 5H, 0
Before
After
W = 0H
5H = 0H
W = 17H
5H = 0H
cont
MOVF f, d
Move the content of f register upon the status of
d
(f) (d)
Affect bit Z of STATUS register
Instruction: MOVF
Before
W = 09AH
FSR = 0H
FSR, 0
After
MOVLW
Instruction: MOVLW
Before
W = 09AH
After
W = 5AH
5AH
MOVWF f
Move data from WREG register to f register
(W) (f)
Not affect bit of STATUS register
Instruction: MOVWF
Before
PORTB = 00H
W = 09AH
PORTB
After
PORTB = 09AH
W = 09AH
ANDLW k
Logical
Instruction: ANDLW
Before
W = A3H
5FH
After
W = 03H
ANDWF f, d
Instruction: ANDWF
Before
W = 17H
FSR = 0C2H
FSR, 1
After
W = 17H
FSR = 02H
BCF
f, b
After
BSF
f, b
After
INTCON = 0BH
INTCON = 08BH
BTFSS f, b
I GOTO LOOP
J
Before
PC = address H
After
PC = Add. J if STATUS<2> = 1,
PC = Add. I if STATUS<2> = 0
BTFSC f, b
I GOTO LOOP
J
Before
After
PC = address H
PC = Add. J if PORTA<3> = 0,
PC = Add. I if PORTA<3> = 1
CALL k
Call subroutine
(PC) + 1 TOS (top of stack)
k PC<10:0>
(PCLATCH<4:3>) PC<12:11>
2-cycle instruction
Not affect on STATUS register
Before
After
PC = add. SO
PC = add. THEN;
TOS = add. SO+1
CLRF f
Clear the content of f register
00h (f)
1 Z
After
PORTA = 00H
Z=1
CLRW
Clear the content WREG register
00h (W)
1 Z
Instruction: CLRW
Before
W = 5AH
After
W = 00H
Z=1
COMP f, d
Complement the content of f register
(f) (d)
After
ONE = 13H
W = 0ECH
DECF f, d
Decrease f register
(f) 1 (d)
After
CNT = 00H
Z=1
DECFSZ f, d
Instruction:
Before
After
PC = add. HERE
CNT = CNT - 1
PC = add. CONT if CNT = 0;
PC = add. HERE + 1 if CNT 0
GOTO k
Unconditional branch
k PC<10:0>
(PCLATCH<4:3>) PC<12:11>
2-cycle instruction
Instruction: HERE
GOTO THERE
THERE
Before
PC = add. HERE
After
PC = add. THERE
INCF f, d
After
SATU = 00H
Z=1
INCFSZ
f, d
Increase the content of f register and skip the next instruction if the
result is 0; otherwise execute the next instruction
(f) + 1 (d), skip if result = 0
2-cycle instruction
Before
After
PC = add. HERE
CNT = CNT + 1
PC = add. CONT if CNT = 0;
else add. HERE + 1
IORLW k
Inclusive OR literal k with the content of WREG
register
(W) OR k (W)
Affect bit Z of STATUS register
Instruction: IORLW
Before
W = 09AH
Z=?
35H
After
W = 0BFH
Z=0
IORWF f, d
Inclusive OR the content of WREG register with f
register
(W) OR (f) (d)
Affect bit Z of STATUS register
Instruction: IORWF
Before
RESULT = 13H
W = 91H
RESULT, 0
After
RESULT = 13H
W = 93H
Z=0
NOP
No operation
Instruction: NOP
RETFIE
Return from interrupt
TOS PC
1 GIE (Global Interrupt Enable)
Not affect bit of STATUS register
Instruction: RETFIE
Before
After
PC = TOS
GIE = 1
RETLW
Instruction: RETLW
Before
W = 09AH
088H
After
W = 088H
RETURN
Return from subroutine
POP the TOS and load into the PC
2-cycle instruction
Instruction: RETURN
Before
After
PC = TOS
RLFf, d
After
RRF f, d
After
SLEEP
00h WDT
0 WDT prescalar
1 TO
0 PD
Affect TO & PD bits of STATUS register
Instruction: SLEEP
SUBLW
Instruction: SUBLW
02H
Before
After
W = 01H
C=?
Z=?
W = 01H
C=1
Z=0
SUBWF f, d
Instruction: SUBWF
02H, 0
Before
After
W = 01H
F = 05H
C=?
Z=?
W = 04H
F = 05H
C=1
Z=0
SWAPF f, d
Exchange the upper & lower nibbles of f register
(f<3:0) (d<7:4>), (f<7:4) (d<3:0>)
Not affect STATUS register
Instruction: SWAPF
Before
ON = 0F4H
W = 09AH
ON, 1
After
ON = 04FH
W = 09AH
XORLW k
Exclusive OR (XOR) the content of WREG
register with k literal
(W) XOR k (W)
Store the result in WREG register
Affect bit Z of STATUS register
Instruction: XORLW
Before
W = 0B5H
0AFH
After
W = 01AH
XORWF f, d
Exclusive OR (XOR) the content of WREG
register with f register
(W) XOR (f) (d)
Affect bit Z of STATUS register
Instruction: XORWF
Before
REG = 0AFH
W = 0B5H
REG, 1
After
REG = 01AH
W = 0B5H
PIC16
Addressing
Modes
Addressing Modes
Direct Addressing
-through a 9-bit address (7 bits of direct address of an
instruction with two bits (RP1, RP0) from STATUS register)
Any access to SFR registers is an example of direct
addressing.
Addressing Modes
Indirect Addressing
-derives it from IRP bit of STATUS and FSR registers.
-Addressed location is accessed via INDF register which
in fact holds the address indicated by a FSR.
One general purpose register (GPR) at
address 0Fh contains a value of 20.
Program
Memory
Considerations
Program memory is
divided into four 2k14
pages
0000h
14-bits
Reset
Reset Vector
Vector
0004h
Interrupt
Interrupt Vector
Vector
Required to maintain
single word/single
cycle execution
0800h
Paging is only a
concern when using
the call or goto
instructions, or when
directly modifying the
program counter
1000h
2k
Page
Page 00
PCH
PCH == 00h
00h
Page
Page 11
2k
Page
Page 22
2k
Page
Page 33
2k
PCH
PCH == 08h
08h
PCH
PCH == 10h
10h
1800h
PCH
PCH == 18h
18h
1FFFh
101 ASP
Slide
89
Program Counter
PCH
Program Counter
PCL
12
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
Interrupts
Instructions: CALL, GOTO, RETURN, RETLW, RETFIE
Any instruction that uses the PCL register as an operand
101 ASP
Slide
90
PC Absolute Addressing
CALL and GOTO Instructions:
13
12
11
Opcode
Opcode
00
00
00
00
00
00
00
00
00
00
00
10
101 ASP
Slide
91
PC Absolute Addressing
14-Bit CALL or GOTO Instruction in Program Memory
13
12
11
Opcode
Opcode
10
00
00
00
00
00
00
00
00
00
00
00
Slide
92
--
--
--
00
00
00
00
00
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
PCH
PCH
PCL
PCL
101 ASP
PC Absolute Addressing
--
--
--
00
00
00
00
00
W Register
13
12
11
Opcode
Opcode
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
MySubroutine
--
00
00
00
00
00
00
00
org 0x0020
movlw
HIGH MySubroutine
movwf
PCLATH
call
MySubroutine
org 0x1250
<do something useful>
return
101 ASP
Slide
93
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
MySub1
MySub2
MySub3
MySub4
movlw HIGH
MySub1
movwf PCLATH
call
MySub1
call
MySub4
bsf PORTB,7
bsf PORTB,0
call
MySub2
return
bsf PORTB,1
call
MySub3
return
bsf PORTB,2
return
bsf PORTB,3
call
MySub2
return
101 ASP
0020
0
1
2
3
4
5
6
7
13-bit x 8-Level
Return Address Stack
Slide
94
PC Relative Addressing
FF
W Register
To write to PC:
Write high byte to
PCLATH
Write low byte to PCL
(PCH will be loaded with
value from PCLATH)
PCLATH
FF
PCH
PCL
FF
movlw
movwf
movlw
movwf
101 ASP
FF
HIGH 0x1250
PCLATH
LOW 0x1250
PCL
Slide
95
PIC MCU
ORG 0x0020
;Page 0
movlw HIGH SevenSegDecode
Example: Use a lookup table
movwf PCLATH
with relative addressing to
movlw .5
retrieve the bit pattern to
call
SevenSegDecode
movwf PORTB
display a digit on a 7segment LED
ORG 0x1800
;Page 3
SevenSegDecode:
addwf PCL,f
retlw b00111111 ;0
retlw b00000110 ;1
retlw b01011011 ;2
retlw b01001111 ;3
retlw b01100110 ;4
retlw b01101101 ;5
retlw b01111101 ;6
retlw b00000111 ;7
retlw b01111111 ;8
retlw b01101111 ;9
2006 Microchip Technology Incorporated. All Rights Reserved.
101 ASP
Slide
96
Simple
operation
Programs
Example 3 :
L2
CLRF TRISB
; Clear TrisB( Port B is made out port)
SETF TRISC
; Set TRISC, (Port C is made Input port)
: MOVF PORT C ,W ; Get data from Port C.
ADDLW 5
; Add literal 5
MOVWF PORT B
; Send it to Port B
BRA L2
; Branch to Loop L2
So , it is clear that unless the TRIS bits are activated by putting a 1 ,the
data will not be transferred to WREG from the port pins of PORT C
UNIT II
INTERRUPTS &
TIMER
UNIT-2 Syllabus
INTERRUPTS AND TIMER
Interrupts: a review
An interrupt is any service request that
causes the CPU to stop its current
execution stream and to execute an
instruction stream that services the
interrupt
When the CPU finishes servicing the
interrupt, it returns to the original
execution stream at the point where it
left off.
Interrupt driven I/O for interfacing with
on chip peripherals
Interrupts in PIC
Sources of interrupt are many
INT pin interrupt from external source
Port B change interrupt (RB7:RB4)
Timer overflow interrupts
USART interrupts
A/D conversion interrupts
LCD interrupt
others
Interrupt Management
Use of register INTCON: Status and
Control
Bit 7: Global interrupt enable
Enables (if set) all unmasked interrupts or
disables all interrupts
Peripheral Interrupts
Managed using PIE and PIR
registers
PIE registers contain bits for
enabling interrupts from individual
peripherals
PIR registers contain flag bits for
individual peripheral interrupts
Bit oriented instructions can be
used to examine and/or
manipulate interrupt control and
Interrupt Processing
When interrupt is responded to
GIE bit is cleared to disable other interrupts
PC is pushed into stack
PC is loaded with 0004h
Save STATUS & W register in temporary
memory locations
In the ISR, source of interrupt is determined
by polling the interrupt flag bit
Interrupt Timing
Interrupt Constraints
Each interrupt source charaterised
by
Minimum time interval between
interrupts from the same source
Maximum time it takes the CPU to
execute interrupt sources handler
Critical Region
A critical region is a sequence of
instructions that must be protected from
an intervening interrupt or produce
erroneous output
In PIC this problem is handled by
Single cycle read-modify-write instructions
xorwf PORTD,F
Port D data read, XORed with W and written
back to port D
Example: Port A
All pins are I/O with associated direction
bits in TRISA
Initialisation code:
clrf STATUS
;bank 0
clrf PORTA
; initialises by clearing
output latches
bsf STATUS, RP0
; select bank1
movlw 0xCF
; value used to initialise data
direction
movlwf TRISA
; PortA<3:0>=input,
<5:4>=output
Programmable prescaler
Synchronised Counter
Timer increments on rising edge of external
clock
External clock is synchronised with internal
phase clock
Asynchronous Counter
Timer increments independent of internal
phase clock
Typical
Application
: Real-time
Clock
Watchdog Timer
Free running on chip RC oscillator which
does not require any external component
A WDT time-out generates a device reset
In sleep mode a WDT time-out causes the
device to wake-up
To avoid unintended device reset,
postscaler has to be changed after
clearing watchdog timer
WDT is enabled/disabled by a device
configuration bit
Capture
Capture mode records value of
timer1 when events like rising
edge or falling edge occurs on pin
CCPx
When capture is made, interrupt
request flag bit is set
Compare
Content of register compared with
Timer1 register pair value
When match occurs, voltage level
at CCPx pin is changed depending
on the value of control bits
PWM
Pulse Width Modulation
Duty Cycle often expressed as a percentage of
the period.
Average DC voltage will be approximately the
same percentage of the on voltage.
Typical uses:
Intensity control
Motor control
Temperature control
PWM Mode
In pulse width modulation mode, CCPx
pin produces up to a 10-bit resolution
PWM output
Since CCPx pin is multiplexed with the port
data latch, the corresponding TRIS bit must
be cleared
PWM: Set up
Steps required for setting up PWM
Establish the PWM period by writing
to PR2 register
Establish the PWM duty cycle by
writing onto CCPRxL &
CCPxCON<5:4> bits
Make CCPx pin an output
Establish TMR2 prescale value and
enable timer by writing to T2CON
Configure CCP module for PWM
operation
LCD Module
Generates timing control to drive LCD panel
Also provides control of pixel data
In-circuit programmer
Serial in-circuit programming support
PIC: Examples
Low End: 12C508
8pin package (DIP)
12bit core - 33 instructions
1us instruction time (Tclk = 4MHz)
512 12bit program memory
25 8bit data memory or registers (File registers)
2 level hardware stack (no interrupts)
5 GPIO pins, 1 input only (25mA source/sink)
Features: Internal pullups, wake up on pin change, internal
oscillator
PIC Examples
Mid Range: 16F876
28pin package (DIP)
14bit core - 35 instructions
200ns instruction time (Tclk = 20MHz)
8,092 14bit FLASH program memory
368 8bit data memory or registers (File registers)
256 8bit EEPROM (nonvolatile) data registers
8 level hardware stack (interrupts enabled)
22 GPIO (20mA source / 25mA 7sink)
Peripherals: 5ch 10bit ADC, USART/I2C/SPI, 16bit & 8bit
timers
Features: Brown out detect, In-Circuit Debugger (ICD)
UNIT III
PERIPHERALS
AND
INTERFACING
UNIT-3 Syllabus
PERIPHERALS AND INTERFACING
I2C Bus For Peripherals Chip Access
Bus Operation
Bus Subroutines
Serial EEPROMAnalog To Digital Converter
UART - Baud Rate Selection
Data Handling Circuit And Initialization
LCD And Keyboard Interfacing
ADC Interfacing
DAC Interfacing
Sensor Interfacing
UNIT IV
INTRODUCTION
TO ARM
PROCESSOR
UNIT-4 Syllabus
INTRODUCTION TO ARM PROCESSOR
ARM Architecture
ARM Programmers Model
ARM Development Tools
Memory Hierarchy
ARM Assembly Language Programming
Simple Examples
Architectural Support For Operating Systems
ARM
179
Introduction
180
ARM Evolution
181
ARM Evolution
ARMv3
V3 introduced 32-bit addressing, and
architecture variants:
ARMv4
Full 64 bit product multiply
instruction as well as 32 bit product
multiply instructions plus load and
store instructions (16 bit)
E.g ARM 7
ARMv5
ARMv6
184
185
Versions:
ARM7TDMI (3-stage)
ARMS, ARM9TDMI (5-stage)
ARM10TDMI ( 6-stage)
186
Pipeline Organization
i
n
s
t
r
u
c
ti
o
n
Fetch
i+1
Decode
Execute
Fetch
Decode
Execute
i+2
Fetch
Decode
Execute
cycle
t+1
t+2
t+3
187t+4
Pipeline Organization
Fetch
Decode
Execute
Buffer/data
Write-back
Stages:
188
INTRODUCTION TO
PHILIPS LPC21xx
189
190
Device information
191
ARCHITECTURE
192
Architectural overview
193
Interrupt
controller
The VIC accepts all of the interrupt request
inputs and categorizes them as FIQ ,
vectored IRQ, and non-vectored IRQ as
defined by programmable settings
1)Fast Interrupt request (FIQ) has the
highest priority.
2) Vectored IRQs have the middle priority.
194
195
Watchdog timer
The
Crystal oscillator
On-chip integrated oscillator operates
with external crystal in range of 1
MHz to 30 MHz
197
Pin description
Pin
Type
Description
PWM1
Output
PWM2
Output
PWM3
Output
PWM4
Output
PWM5
Output
PWM6
Output
10-bit A/D
converter
Two 10-Bit Successive
Approximation ADCs, 8 channels
each
Measurement range of 0 V to 3.3
V.
199
Type
Description
AD0.7:0
&
AD1.7:0
Input
VREF
VDDA, VSSA
Power
Register description
Generic
Name
Description
Acces
s
ADCR
R/W
ADGDR
R/W
ADSTAT
ADGSR
WO
ADINTE
N
ADDR0
ADDR1
ADDR2,
3,
4,5,6,7
SAME DESCRIPTION
202
203
Pin description
Pin
Type
Description
AOUT
Output
VREF
Reference
VDDA,
VSSA
Power
DAC Register
This read/write register includes the digital value to be converted to
analog, and a bit that trades off performance vs. power. Bits 5:0 are
reserved for future, higher-resolution D/A converters.
Bit
5:0
15:6
VALU
E
16
BIAS
0
1
31:17 -
Bits 19:18 of the PINSEL1 register (PINSEL1 - 0xE002 C004) control whether
the DAC is enabled and controlling the state of pin P0.25/AD0.4/AOUT.
206
207
Pin
connect
block
The pin connect block allows
selected pins of the
microcontroller to have more
than one function.
Configuration registers
control the multiplexers to
allow connection between the
pin and the on chip
peripherals.
208
PINSEL0 - 0xE002C000
The PINSEL0
register controls
the functions of
the pins as per the
settings listed
The direction
control bit in the
IODIR register is
effective only when
the GPIO function
is selected for a
pin.
209
PINSEL0 - 0xE002C000
210
PINSEL1 - 0xE002C004
211
PINSEL1 - 0xE002C004
212
PINSEL2 - 0xE002C014
213
Pin
Input Description
/
Outp
ut
P0.0-P.31
P1.16-P1.31
Input/
Output
( 48 GPIO)
PORT1 has up to 16 pins available
for GPIO functions.
Pin
Description
Acces
s
R/W
IOPIN
IOSET
(IO0SE
T,IO1S
ET)
R/W
IODIR
(IO0DI
R,
IO1DIR
)
R/W
IOCLR
(IO1CL
W/O
/*SquareWave.c This program will produce a square wave of approximately 1 KHz on Pin 3 of connector JP3. It is
timed using adelay loop. */
#include <Philips\LPC2138.h>
#define CRYSTAL_FREQUENCY_IN_HZ 14745600
#define PLL_MULTIPLIER
#define DEL_LOOPS
CRYSTAL_FREQUENCY_IN_HZ*PLL_MULTIPLIER/86172
#define PIN
0x00008000
#define IODIR
IO0DIR
IO0CLR
#define IOSET
IO0SET
void delay()
{ unsigned i;
void main ( )
{
PINSEL0=0;
PINSEL1=0;
PINSEL2=0;
IODIR=PIN;
IONDIR=0;
for(;;) {
IOCLR=PIN;
delay();
IOSET=PIN;
delay();
}}
216
UARTs
217
Pin
Type
Description
RXD0
Input
TXD0
Output
Register description
Name
Description
Access
U0RBR
RO
U0THR
WO
218
Pin
Type
Descripti
on
SDA0,1
Input/Output
I2C Serial
Data.
SCL0,1
Input/Output
I2C Serial
Clock.
220
consist of 2 timer
A 32-bit Timer/Counter with a
programmable 32-bit Prescaler.
221
UNIT V
ARM
ORGANIZATION
UNIT-5 Syllabus
ARM ORGANIZATION
ARM Instruction
Set
227
Instruction Set
ARM
THUMB
228
Features:
Load/Store architecture
Conditional execution
229
EQ
Conditional execution:
16 condition codes:
equal
NE
not equal
CS
unsigned
higher or
same
CC
unsigned
HI
unsigned
higher
positive or
zero
LS
unsigned
lower or
same
overflow
signed
GE greater than AL
or equal
MI
negative
PL
VS
VC
no overflow
LT
signed less
GT
signed
greater than
LE
signed less
than or
equal
230
NV
always
special
Data transfer
instructions
Branching instructions
Multiply instructions
Software interrupt
instructions
231
Data Processing
Instructions
Arithmetic operations:
MOV, MVN
Comparison operations:
3-address format:
Arithmetic
Operations
Operations are:
ADD operand1 + operand2
ADC operand1 + operand2 + carry
SUB operand1 - operand2
SBC operand1 - operand2 + carry -1
RSB operand2 - operand1
RSC operand2 - operand1 + carry - 1
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Examples
ADD r0, r1, r2
SUBGT r3, r3, #1
RSBLES r4, r5, #5
Comparisons
Logical Operations
Operations
are:
AND operand1
AND operand2
EOR operand1 EOR operand2
ORR operand1 OR operand2
BIC operand1 AND NOT operand2 [ie
bit clear]
Syntax:
<Operation>{<cond>}{S}
Operand2
Examples:
AND r0,
r1, r2
BICEQ r2, r3, #7
Rd, Rn,
Data Movement
Operations
are:
MOVoperand2
MVN
NOT operand2
Operand2
Examples:
MOVr0,
r1
Rd,
Data Transfer
Instructions
Load/store instructions
LDR
Load Word
STR
Store Word
LDRS
H
LDRB
STRS
H
STRB
LDRS
STRS
Store Signed
Byte
237
Block Transfer
Instructions
Load/Store Multiple
instructions (LDM/STM)
Whole register bank or a
subset
copied to memory or
restored
with single instruction
LDM
R0
Mi
Mi+1
Mi+2
R1
R2
Mi+14
Mi+15
R14
STM
R15
238
Branching Instructions
239
More traditional:
Access to R0 R8 restricted to
No condition codes
Two-address data processing instructions
MOV, ADD, CMP
241