SETUP-HOLD

Analysis
1

SETUP SIMULATION.
Details of Simulation parameters DESIGN-SDFSND1BWP
PROCESS- 40LP
Vendor- TSMC
The different methods to find out Setup-time is as
follows1. Manual Sweep - In this simulation the data
edge is varied from infinite setup time to very
close to the clock edge. The output Q is
monitored until it fails. The latest edge that
passed is the setup time.
Setup-time
CK2q_delay
DIFF
Results - 4.50E-11
9.52E-11
0%
3.50E-11

9.89E-11

4%

2.50E-11

1.43E-10

44%

1.50E-11

failed

failed

Manual Sweep Method

2. PASS-FAIL METHOD- In this method the

PassFail optimization algorithm from Hspice is used
to find out the setup time. The only risk in this
method is the setup time obtained is too optimistic
and may fail in Silicon.
ResultsSetup Time=24.71 ps & Ck2Q_delay= 2.023e10 s.

PASS-FAIL METHOD

3. Delay-Degradation Method- In this method

the setup time is calculated when the Clock to Q
delay degrades by 10%. This gives a pessimistic
values and is often the preferred method in liberty
characterization.
Results
Setup-time=
32.46ps
Ck2Q_delay_ref= 7.860e-11 s
10% increase in
delay.
Ck2Q_delay=
8.648e-11 s
6

DELAY-DEGRADATION
METHOD