Implementation of Basic

Digital Filter Structures

R.C. Maher
ECEN4002/5002 DSP Laboratory
Spring 2003

Digital Filters
DSP ALUs designed to do fast MACs
Use Harvard architecture: place filter state
in X memory, filter coefficients in Y
memory
Try to avoid truncation until after all MACs

ECEN4002

Filter Implementation

FIR Filter Review

x[n]
Z-1

h0

x[n1]

Z-1

h1

x[n2]

Z-1

h2

x[n-3]

y[n]

h3
3

H ( z ) hn z n
n0

ECEN4002

Filter Implementation

FIR Setup
X Memory

Modulo N
Buffer
Memory

Input

Y Memory

Filter state

Coefficients

(delay line)

(delay line)

Accumulator
ECEN4002

Filter Implementation

Modulo N
Buffer
Memory

Output
4

FIR Code for 56300

Filter order n
Input and Output in accumulator a
r0: samples, r4: coefs, m0 & m4: n-1
move
clr
rep
mac
macr

a,x(r0)
a
#n-1
x0,y0,a
x0,y0,a

ECEN4002

x:(r0)+,x0

y:(r4)+,y0

x:(r0)+,x0
(r0)-

y:(r4)+,y0

Filter Implementation

IIR Filters
IIR (infinite impulse response) filters allow
zeros and poles; FIR allow zeros only. IIR
can be more selective for a given filter order
IIR also called recursive filters: output
depends on past inputs and past outputs
IIR designs are not guaranteed to be stable
IIR filters can be particularly sensitive to
coefficient quantization
ECEN4002

Filter Implementation

IIR Issues: Stability and

Sensitivity
Finite precision of coefficients can lead to
several issues:
In order to be unconditionally stable and causal,
all system poles must be inside the unit circle (|
z|<1). Coefficient roundoff may inadvertently
move a pole outside unit circle
Finite coefficient precision quantizes pole
locations: may change frequency response
from ideal case even if still stable
ECEN4002

Filter Implementation

Overflow Issues
Gain from input to storage nodes in the
filter may exceed unity. This can cause
filter state to be saturated (clipped),
resulting in distortion
Typically must scale down (attenuate) the
input signal, then scale up (amplify) by an
equal amount on the output
ECEN4002

Filter Implementation

Second-Order Sections
High-order filter polynomials involve terms
that are products and sums involving many
poles and zeros. Small roundoff errors
when implementing filter can lead to large
response errors
As with analog filters, it is typical to reduce
sensitivity by using second-order sections
ECEN4002

Filter Implementation

Implementing 2nd Order Sections

2nd Order (bi-quad) expression

b0 + b1 z 1 + b2 z 2
H z =
1 + a1 z 1 + a2 z 2
1 + k1 z 1 + k 2 z 2
= b0
1 + a1 z 1 + a2 z 2
Numerator implements 2 zeros, denominator
implements 2 poles (real or complex conj.)
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Filter Implementation

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Direct Form Bi-Quad

x[n]
Z
x[n1]

-1

b0

y[n]

Z-1
y[n-1]

Z-1

x[n2]

ECEN4002

b1
b2

Filter Implementation

-a1

Z-1
y[n-2]

-a2

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IIR Code for 56300

Direct Form II, with equations:
w(n)=x(n)-ai1w(n-1)-ai2w(n-2)
y(n)=w(n)+bi1w(n-1)+bi2w(n-2)

Since ai1 and bi1 may be > 1, need to divide

all coefs by 2, then use special scaling mode
for 2 on read from accumulator:
ori
#$08,MR
sets scale up: 1-bit left shift on acc read
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Filter Implementation

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IIR for 56300 (cont.)

N = number of second-order sections
Filter state (w) in X memory: r0
Filter coefs (a,b) in Y memory: r4
Coefs stored in order:
a12/2, a11/2, b12/2, b11/2, a22/2, bN2/2

State (data) stored in order:

w1(n-2), w1(n-1), w2(n-2), w2(n-1), wN(n-1)

m0 = 2*N-1, m4 = 4*N-1
Initial gain in y1, input in y0, output in a
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Filter Implementation

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IIR for 56300 (cont.)

mpy y0,y1,a
x:(r0)+,x0
y:(r4)+,y0
do #N,end_cell
mac -x0,y0,a x:(r0)-,x1
y:(r4)+,y0
macr -x1,y0,a x1,x:(r0)+
y:(r4)+,y0
mac x0,y0,a
a,x:(r0)+ y:(r4)+,y0
mac x1,y0,a
x:(r0)+,x0
y:(r4)+,y0
end_cell
rnd a

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Filter Implementation

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Other Filter Structures

Direct Form I and Direct Form II

Cascade and Parallel Realizations
Transpose Forms
Lattice Forms

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Filter Implementation

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EVM Note: External Memory

To use external memory on EVM, need to
program the bus control register and the address
attribute register 0 (see 56300 Family Manual)
movep

#$040821,x:M_AAR0

movep

#$012421,x:M_BCR

;Compare 8 most significant bits

;Look for a match with address
;Y:0000 0100 xxxx xxxx xxxx xxxx
;No pack, no mux, Y enabled
;P and X disabled
;AAR0 pin active low
;One ext. wait state

Access to external memory is slower than internal

memory: wait state stalls processor
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Filter Implementation

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Conclusion
DSP chips (including the DSP563xx) are
designed specifically for fast digital filter
implementations
Care must be taken to ensure that the
practical details are addressed:
Coefficient quantization
Overflow and scaling
Computational complexity
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Filter Implementation

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