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MSP430 Family Msp430 Cpu Memory MSP430 Peripherals Launchpads
MSP430 Family Msp430 Cpu Memory MSP430 Peripherals Launchpads
MSP430
Family
MSP430 CPU
Memory
MSP430 Peripherals
Launchpads
MSP430 Families
Low Power
+
Performanc
e
Ultra
Low
Security
+ Comm
MSP430FR58xx/59xx
MSP430FR58/59xx
Ultra Low Power
16-bit MCU
16MHz
Memory
FRAM
(32/48 / 64
KB)
RAM
(1 or 2 KB)
Debug
MPU
Real Time JTAG
Embedded emulation
Bootstrap Loader
Accelerators
32x32 Multiplier
DMA (3 Ch)
CRC16
AES256 Encryption
Serial
Interfaces
(FR59xx)
3 Serial Interfaces
(eUSCI)
2 UART + IrDA or SPI
2 I2C or SPI
Analog
12-bit SAR ADC (up to
16 ch)
o Differential inputs
o Window comparators
Comparator (Comp_E)
Vref (REF_A)
Timers
Watch Dog Timer (WDT_A)
Real Time Clock (RTC_B)
Two 16-bit w/3 CCR (TA0,
TA1)
Two 16-bit w/2 CCR (TA2,
TA3)
Connectivity
One 16-bit w/7 CCR (TB0)
Up to 40 GPIO
(Interrupt/Wake)
Power
Cap touch
IO
& Clocking
Brownout Reset
Supply Voltage Supervisor
(SVS)
Low Power Vreg (1.5V LDO)
External Oscillators: LFXT,
MSP430 CPU
No paging
Page-free 20-bit reach
Improved code density
Faster execution
F5529 Memory
Map
Bytes
Memory
U
Use
se for
for your
your own
own
calibration
calibration data,
data,
etc.
etc.
4
(ABoot
Loader
4 segments
segments
(A(BSL)
D)
(BSL)
D)
Program
128
128 byte
byteFlash/RAM
Program
Flash/RAM
segments
with
serial
segments
with
serial
(slau319)
Flash
0xFFF
F
0xFF8
INT Vectors
0
0x240
0
0x01C
0
128
K
80
RAM
8K
USB RAM
2K
4K
MSP430
MSP430
Memory
Memory
Unified
Unified memory
memory
map
map
(program
(program or
or
data)
data)
Absolutely no
Absolutely no
paging
paging
RAM
Always
Always aa contig.
contig.
block
block
If
If enabled,
enabled, USB
USB
port
port uses
uses first
first 2K
2K
RAM
RAM segments
segments
can
can be
be powered
powered
down
Device
down
Device
Descriptors
Descriptors (TLV)
(TLV)
Factory
Factory calibration
calibration
data,
data, periph
periph
F5529
0x243F
F
0xFFFF
Main
Flash
Main
Flash
RAM
USB RAM
TLV
Info A
Info B
Info C
0x180
0
Info D
Boot Loader
FR5969
Most MSP430
devices have similar
Memory Maps
F5529
Main
FRAM
17K
INT Vectors
80
Main
FRAM
47K
8K
2K
Vacant
RAM
TLV
Info A
Info B
Info C
Info D
Boot Loader
Peripherals
128
128
128
128
2K
4K
0x000
Peripherals
0
Bytes
FR5969
64K of non-volatile
FRAM memory
2K of SRAM
MSP430 Peripherals
Clocks
Power Watchdog
GPIO
USB
GPIO
(Chapter
(Chapter 3)
3)
Independently
Independently
programmable
programmable
Any
Any combination
combination of
of input,
input,
output,
output, interrupt
interrupt and
and
peripheral
peripheral is
is possible
possible
Each
Each I/O
I/O has
has an
an
individually
individually programmable
programmable
pull-up/pull-down
pull-up/pull-down resistor
resistor
Many
Many devices
devices can
can lock
lock pin
pin
values
values during
during low-power
low-power
GPIO
Timers
(Chapters
(Chapters 3,
3, 5,
5, 6,
6, 8)
8)
Timer_A:
Timer_A: 16-bit
16-bit timer/counter
timer/counter
Multiple
Multiple capture/compare
capture/compare registers
registers
Generates
Generates PWM
PWM and
and other
other complex
complex
waveforms
waveforms && interrupts
interrupts
Directly
Directly trigger
trigger GPIO,
GPIO, DMA,
DMA, ADC,
ADC, etc.
etc.
Timer_B:
Timer_B: Same
Same as
as A;
A; improved
improved PWM
PWM
Timer_D:
Timer_D: Same
Same as
as B;
B; with
with hi-res
hi-res timing
timing
RTC:
RTC: Real-time
Real-time clock
clock with
with calendar
calendar &&
alarms
alarms runs
runs in
in LPM3
LPM3 low
low power
power mode
mode
Power
Clocking
(Chapter
(Chapter 4)
4)
Three
Three Internal
Internal Clocks
Clocks
provide
provide for
for CPU,
CPU, fast
fast and
and
slow
slow peripherals
peripherals
Many
Many clock
clock sources
sources
(internal
(internal and
and external)
external)
provide
provide cheap
cheap and
and
accurate
accurate clks
clks with
with quick
quick
wake-up
wake-up
Clock
Clock defaults
defaults and
and
failsafes
failsafes improve
improve system
system
robustness
robustness
Power Mgmt
MSP430 Analog
Clocks
Power Watchdog
Analog
Families
Families ADC
ADC converter
converter
options:
options:
10
10 or
or 12-bit
12-bit SAR
SAR (ADC10,
(ADC10, ADC12)
ADC12)
16
16 or
or 24-bit
24-bit Sigma-Delta
Sigma-Delta (SD16,
(SD16, SD24)
SD24)
Slope
Slope converters
converters
DAC
DAC converters:
converters: 12-bit
12-bit DAC12
DAC12
Comparators
Comparators
Voltage
Voltage REFerences
REFerences
Features
Features in
in common:
common:
F5529 block
diagram
Analog
input
Analog mux
mux supporting
supporting multiple
multipleCH
input6chans
chans
DMA
without
DMA can
can read/write
read/write samples
samplesTimers
without CPU
CPU
Precise
Precise timing
timing when
when using
using timer
timer to
to trigger
trigger
GPIO
MSP430 Communication
Clocks
Power Watchdog
Communications
USB
USB
USB
USB 2.0
2.0 at
at Full
Full speed
speed (12Mbps)
(12Mbps)
Includes
Includes PHY,
PHY, LDO,
LDO, PLL,
PLL, PUR
PUR
Serial
Serial ports
ports
USI:
USI:
USCI:
USCI:
eUSCI:
eUSCI:
SPI,
SPI, I2C
I2C
SPI,
SPI, I2C,
I2C, IrDA,
IrDA, UART
UART
enhanced
enhanced USCI
USCI
F5529
block
Radio
Frequency
Radiodiagram
Frequency
CH 6
CC430
include
CC430 and
and RF430
RF430 devices
devices
include
Timers
Sub-1GHz
Sub-1GHz or
or NFC
NFC radios
radios
GPIO
USB
MSP430 Accelerators
Clocks
Power Watchdog
CH 5
GPIO
C
Accelerators
DMA
DMA (hardware
(hardware
memcpy)
memcpy)
Copy
Copy from
from memory
memory to
to
memory
memory
Faster
Faster copies
copies than
than with
with
CPU
CPU
Supports
Supports periphs
periphs (ADC,
(ADC,
UART)
UART)
MPY32
MPY32 (8/16/32
(8/16/32
Multiplier)
Multiplier)
MAC,
MAC, fractional,
fractional, saturation
saturation
support
support
CRC:
CRC: Single-cycle
Single-cycle CRC
CRC
generation
generation
F5529 block diagram
AES:
AES: 128,
128, 192,
192, 256
256 bit
bit
encryption
encryption
LCD:
LCD: Automatic
Automatic with
with up-to
up-to
USB
MSP-EXP430F5529LP Overview
Register Sets
Pull-up Resistor
Pull-down Resistor