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DLC 4
DLC 4
DLC 4
FPGA
:
: ,
2013/3/28
FPGA
NcuEE
You
can verify your designs at any time by configuring the FPGA devices on
board via the download cable or hardware programmer.
FPGA Architecture
NcuEE
NcuEE
NcuEE
NcuEE
Input,output or bidirectional
Direct or registered(or latched input)
Tri-State output
Programmable slew rate
Programmable thresholds
Programmable Interconnects
NcuEE
CLB
1
10
11
12
13
14
15
16
17
18
19
20
Switch
Matrix
CLB
Switch
Matrix
CLB
CLB
Switch Matrix
General Purpose Interconnect
NcuEE
NcuEE
1.
Design Entry
in Schematic , Verilog and/or
VHDL
2.
3.
Implementation
includes translation , Placement &
Routing and bitstream generation
Download
directly to the Xilinx hardware
device(s) with Slave serial mode
NcuEE
1.
FileProjectName
C:\documents and
setting\ncuee
10
NcuEE
2. FPGA
11
NcuEE
3. Graphic
12
NcuEE
4. Enter Symbol
C:\maxplus2\max2lib\prim
C:\maxplus2\max2lib\mf
C:\maxplus2\max2lib\mega_lpm
5.
13
NcuEE
AND
14
5.a Save & Compile
NcuEE
15
NcuEE
5.b Compile
Compile
Warning Error
16
NcuEE
6.
MAX+plus II
Waveform Editor
17
NcuEE
7.
a. Insert Node
b. List Pin
7.
Pin
18
NcuEE
8.
19
FPGA
NcuEE
1 FPGA
2
3
4 LED
5
NcuEE
LED
A1~A4 B1~B4 Cin
FPGA
V6
AB1
U7
AA2
Y5
AA5
W5
W6
Y6
AB6 Y4 V7 V8 W7 AA7 Y7
LED
NcuEE
LED(
LED )
AA18 Y18 Y19 W18 AA20 U17 Y20 AB22
NcuEE
Pin Assignment
MAX+plus IIFloorplan Editor
FPGA
NcuEE
Assign
A1
V6
,V6
[A1@V6(I/O)]
Compile
NcuEE
NcuEE
1
1. project
2. FPGA
FPGA LED
NcuEE
27
Half-adder
NcuEE
NcuEE