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TMP - 31157-EMITTER and Pot Devider Bias1448946595
TMP - 31157-EMITTER and Pot Devider Bias1448946595
CONFIGURATION
Emitter Resistor
Improves Bias
Stability
DC equivalent:
1
2
Advantage: Improved Bias stability
against temperature variations:
T ICEO IC IE IE RE
IB IC
Disadvantage: Increased power
consumption, Reduction in voltage
gain (can be minimized by using a
capacitor across RE: Emitter bypass
capacitor CE) 3
Example
4
VOLTAGE-DIVIDER BIAS
CONFIGURATION
More flexibility in
design
RB is replaced by R1-
R2 voltage divider
network
Analysis is
complicated
Use Thevenins
Theorem 5
DC
Equivalent
Circuit
Find
Thevenin
s
equivalent
for series
connectio
n of VCC- 6
Solving input loop:
7
Example:
Determine the dc bias voltage VCE
and the current IC for the voltage
divider configuration of Fig.
8
Summary: BJT DC Biasing