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2nd Review PPT (521) Final
2nd Review PPT (521) Final
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Contents
Plan of action
Objective
Introduction
Block diagram of ROBA multiplier
Implementation of ROBA multiplier
Parallel Prefix Adder:Kogge stone adder
Block diagram of proposed system
RTL and Technology schematic
Simulation results of kogge stone adder, ROBA multiplier with KS adder,
FIR filter design
Work to be completed
Tools to be used
References
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Plan of Action
S.No. Project Work to be carried out No. of
Weeks
1. Literature Survey 6
2. Implementation of ROBA multiplier 4
3. Design of FIR filter using ROBA Multiplier 4
4. Coding and verification results 8
5. Comparison of various multipliers 8
6. Writing paper for publication 4
7. Documentation 2
Total 36
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Objective
The main objective of the project is to analyze the
performance of ROBA multiplier for DSP filtering.
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Block Diagram of Proposed System
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Introduction
The performance of a traditional arithmetic circuit has limits. In order to
further enhance performance , approximate arithmetic designs scarify accuracy
to reduce energy consumption and reduce the cost.
These approximate arithmetic designs can be used in error tolerance
applications or applications related to speech and image.
Multipliers are one of the primary sources of power consumption in DSP
applications such as FIR filters.
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Block diagram of ROBA Multiplier
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Implementation of ROBA Multiplier
The ROBA multiplier, which had high accuracy, was based on rounding of the
inputs to the form of 2n.
The multiplication of A by B may be rewritten as
In Fig.1 First, the signs of the inputs are determined, and for each negative
value, the absolute value is generated. Next, the rounding block extracts the
nearest value for each absolute value in the form of 2 n . Having determined the
rounding values, using three shifter blocks, the products Ar Br, Ar B, and
Br A were calculated.
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The input bit width of the shifter blocks is n, while their outputs are 2n. A
single 2n-bit kogge stone adder is used to calculate the summation of Ar B
and Br A.
The output of this adder and the result of Ar Br are the inputs of the
subtractor block whose output is the absolute value of the output of the
proposed multiplier.
Finally, if the sign of the final multiplication result should be negative, the
output of the subtractor will be negated in the sign set block. To negate the
values, twos complement representation was used.
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Parallel Prefix Adders(PPA)
Parallel prefix (or tree prefix) adders provide a good theoretical basis to make
a wide range of design trade-offs in terms of delay, area and power. Parallel
Prefix Adders (PPA) is designed by considering carry look adder as a base.
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1. GP block:
The generate and propagate block takes a pair of operand bits (a, b) as
inputs. Computes a pair of generate and propagate signals (g, p) as output.
Generate (Gi) indicates whether a carry is generated from that bit
Gi = Ai & Bi
Pi = Ai xor Bi
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2. BC block:
The black cell takes two pairs of generate and propagate signals (gi, pi) and (gj, pj)
as input. computes a pair of generate and propagate signals (g, p) as output
Gi.j = Gi + (Pi . Gj)
Pi.j = Pi . Pj
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3. GC block:
The gray cell takes two pairs of generate and propagate signals (Gi, Pi) and (Gj, Pj)
as inputs. Computes a generate signal G as output
Gi,j = Gi + (Pi . Gj)
Black Cell consists of both Generate and propagate where as Gray Cell consists
of Generate.
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Architecture of Kogge Stone Adder
A 16-bit Kogge-Stone adder is built from 16 generate and propagate (GP) blocks,
37 black cells (BC) blocks, 16 (GC) blocks, 16 sum blocks. Kogge-Stone prefix
tree is one of the adders that use fewest logic levels.
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Figure 5: Example for kogge stone adder
FIR filter design
In signal processing, there are many instances in which an input signal to a
system contains extra unnecessary content or additional noise which can
degrade the quality of the desired portion.
In such cases, we may remove or filter out the useless samples. Therefore,
common filtering objectives are to improve the quality of a signal, to extract
information from signals or to separate two or more signals previously
combined to make efficient use of an available communication channel.
In the FIR system, the impulse response is of finite duration, this means that it
has a finite number of nonzero terms .
The response of the FIR filter depends only on the present and past input
samples.
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FIR filter was designed and simulated using integer coefficients.
Corresponding equation for the FIR filter is
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Technology Schematic of ROBA multiplier:
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RTL schematic of FIR filter using ROBA multiplier
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Simulation result of Kogge stone Adder
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Simulation results for Gray and black cells
Figure 14: Simulation result for ROBA multiplier with Kogge stone Adder 25
Simulation result for FIR filter using ROBA multiplier
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Work to be Completed
FIR filter for speech signal application has to be implemented using ROBA
multiplier and power,speed and area analysis has to be done for the
implemented design.
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Tools used
Software:
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References
[1] Reza Zendegani; Mehdi Kamal; Milad Bahadori; Ali Afzali-Kusha; Massoud
Pedram,"RoBA Multiplier: A Rounding-Based Approximate Multiplier for High
Speed yet Energy-Efficient Digital Signal Processing IEEE Trans. Very Large Scale
Integr. (VLSI) Syst.,pp.1-9, July 2016.
[2] A. Momeni, J. Han, P. Montuschi, and F. Lombardi, Design and analysis of
approximate compressors for multiplication, IEEE Trans. Comput., vol. 64, no. 4,
pp. 984994, Apr. 2015.
[3] K. Bhardwaj, P. S. Mane, and J. Henkel, Power&area-efficient approximate wallace
tree multiplier for error-resilient systems, in Proc. 15th Int. Symp. Quality Electron.
Design, 2014, pp. 263269.
[4] Cong Liu; Jie Han; Jie Han,A Low-Power, High-Performance Approximate
Multiplier with Configurable Partial Error Recovery, IEEE Trans. Very Large Scale
Integr. (VLSI) Syst.,pp.33-37, March 2014.
[5] F. Farshchi, M. S. Abrishami, and S. M. Fakhraie, New approximate multiplier for
low power digital signal processing, in Proc. 17th Int. Symp. Comput. Archit. Digit.
Syst. (CADS), Oct. 2013, pp. 2530.
[6] P. Kulkarni, P. Gupta, and M. Ercegovac, Trading accuracy for power with an
underdesigned multiplier architecture, in Proc. VLSI Design, 2011, pp. 346351.
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[7] V. Gupta, D. Mohapatra, S. P. Park, A. Raghunathan, and K. Roy, IMPACT:
Imprecise adders for low-power approximate computing, in Proc. ISLPED, 2011,
pp. 409414.
[8] A. Sampson, W. Dietl, E. Fotuna, D. Gnanapragasam, L. Ceze, and D.
Grossman, EnerJ: Approximate data types for safe and general lowpower
computation, in Proc. PLDI, 2011, pp. 164174.
[9] D. Mohapatra, V. K. Chippa, A. Raghunathan, and K. Roy, Design of voltage-
scalable meta-functions for approximate computing, in Proc. DATE, 2011, pp. 1
6.
[10] R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan, MACACO:
Modeling and analysis of circuits for approximate computing, in Proc. CAD, 2011,
pp. 667673.
[11] H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, Bio-inspired
imprecise computational blocks for efficient vlsi implementation of applications,
IEEE Trans. Circuits Syst. I, vol. 57, no. 4, pp. 850862, 2010.
[12] K. Khaing Yin, G. Wang Ling, and Y. Kiat Seng, Low-power high speed
multiplier for error-tolerant application, in Proc. EDSSC, 2010, pp. 14.
[13] Z. Ning, G. Wang Ling, Z. Weija, Y. Kiat Seng, and K. Zhi Hui, Design of
low-power high-speed truncation-error-tolerant adder and its application in digital
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signal processing, IEEE Trans. VLSI Syst., vol. 18, no. 8, pp. 12251229, 2010.
Thank you
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