Instructions: Language of the

Computer- Chap 2
Instruction Set Architecture
Register Architectures
General-Purpose Register Architecture
Register-Memory Architecture
Load-Store or Register-Register Architecture
Accumulator Architecture
Compact Code and Stack Architecture

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Single Register Architecture

Early machines
based on single
register
Supports single/zero
address instructions
Arithmetic
instructions require
memory access
Short instruction
Memory traffic high
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Single Register Architecture
A=B+C
A, B & C are memory addresses
load B
add C
store A
load regA, memoryX not allowed
Complex operations too slow

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Stack Architecture

Simple expression
evaluation
Short instruction
yields good code
density
Stack can not be
randomly accessed
Inefficient stack is a
bottleneck

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Stack Architecture
A=B+C
A, B & C are memory addresses
push B
push C
add
pop A
Stack based m/c requires low memory

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General-Purpose Architecture

Most general model

for code generation
All operands must
be named, leading
to longer code
Register-register
m/c
Register-memory
m/c

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General-Purpose Architecture
A=B+C
A, B & C are memory addresses
load R1, B load R1, B
load R2, C add R1, C
add R1, R2 store A, R1
store A, R1

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Example
a=b+cd
Accumulator Architecture Stack
Architecture

General Purpose Register (Register to Register)

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Example
a=b+cd
Accumulator Architecture Stack
Architecture
Load b push d
Add c push c
Sub d push b
Load a add
sub
pop a

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Example
a=b+cd
General Purpose Register (Register to Register)
Load R1, b
Load R2, c
Add R1,R2
Load R2, d
Sub R1, R2
Store R1, a

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Instructions & Instruction Set
Instructions: Words
Instruction Set: Vocabulary
Primitive & Restrictive
Relationship between HL Programming and
hardware through Instruction set
MIPS processor

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Instruction Operands
All MIP Arithmetic instructions have three
operands
Operand order is fixed
Destination, source, source
Other MIP instructions have zero, one or two
operands

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Adding four variables
C Code: a=b+c+d+e
MIPs Code: add a, b, c
add a, a, d
add a, a, e
Variable number of operands leads to complex
hardware
Design Principle 1
Simplicity favours Regularity

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Compiling C instruction to MIP
a = b + c; add a, b, c
d = a e; sub d, a, e

f = (g + h) (i + j);
add t0, g, h
add t1, i, j
sub f, t0, t1

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C variables vs. MIP Registers
Operands of HLL Arithmetic Instructions are
variables
Operands of MIP Arithmetic Instructions are
registers
32-bit MIP register
Limited number of registers
MIP has 32 registers
Design Principle 2
Smaller is Faster

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MIP instructions using Registers
a = b + c; add $s1, $s2, $s3
d = a e; sub $s4, $s1, $s5

f = (g + h) (i + j);
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1

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Implementing Data Structures
Programming languages support complex
data structures
Arrays, Queues, Stack Data Structures require
large storage space
Limited Registers
Implement Data Structures in Memory
Data Transfer Instructions
Load: Transfer data from memory to register
Store: Transfer data from register to memory

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MIP Memory

MIP memory organized as 32-bit word

Byte Addressing
Alignment Restriction
Big Endian

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Byte Ordering (Endianness)
Layout of multi-byte operands in memory

Little endian (x86)

Least significant byte at lowest address in
memory
Big endian (most other ISAs)
Most significant byte at lowest address in
memory

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Another view of Endianness
At word address 100 (assume a 4-byte word)
long a = 11223344;
big-endian (MSB at word address) layout

100 101 102 103

100 11 22 33 44

little-endian (LSB at word address) layout

103 102 101 100
11 22 33 44 100

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