SHRI KRISHNAA COLLEGE OF

ENGINEERING AND TECHNOLOGY

FULLY PIPELINED COLOR

DEMOSAICKING VLSI
DESIGN
UNDER THE GUIDANCE OF,
PRESENTED BY,
S.SEENUVASAMURTHI
S.NISHANTHI
R.SUBALAKSHMI
S.JAKIRABANU
OVERVIEW

Objective
Abstract
Existing work
Proposed work
 INTRODUCTION:

This paper presents fully pipelined color demosaicking design.

Most digital cameras capture imagery with a color filter array
(CFA), sampling only one color value for each pixel.
Afterwards, interpolating other two missing color values.
This interpolation process is known as demosaicking.
In this paper, pipelining concept is introduced to increase the
processing speed of the color interpolation algorithm.
The proposed algorithm consists of pipelining stage.
THEME OF THE PROJECTS:

To improve a high quality reconstructed images.

 CFA:

In digital camera, the digital image is captured by single

CCD (Charge Couple Device) or CMOS (Complementary
Metal Oxide Semiconductor) sensor whose surface is
covered with a color filter array (CFA).
Single sensor is able to capture a single color component
so three sensors required to sample the red (R), green (G),
blue (B) value for complete color image.
In order to reduce the cost and size, most digital camera
used single sensor instead of three with help of color filter array technique.
The color filter array contain set of filters that are arranged in interleaving pattern. so each
pixel sensor sample one color of primary three color.
This means the camera must estimate other two missing color values at each pixel.
The most commonly used color filter array is the Bayer color filter array or bayer pattern.
Example of CFA:
Block diagram:
Boundary detector and mirror:

A boundary detector and a boundary mirror machine were added to improve the
quality of pixels located in boundaries
The boundary detector is designed to provide a flag signal to the boundary mirror
machine to determine whether the location of the target pixel is within the boundary
region or not.
If the location is within the boundary range, the boundary mirror machine will provide
the missed CFA values in the boundary region by a mirror technique. Moreover, six
extra shift registers were added to store the information of the mirror CFA pixels for
hardware sharing M1 and M3.
 PROPOSED COLOR DEMOSAICKING
ALGORITHM:

Green Color Interpolation:

Gi,j =1/2(Gi,j1+Gi,j+1)+1/2RBi,j1/4(RBi,j2+RBi,j+2).
RedBlue Color Interpolation:
RBi,j(BR)G=1/4(RBi1,j1+RBi1,j+1+RBi+1,j1+RBi+1,j+1)+Gi,j1/8[(Gi1,j1+Gi1,j+1+Gi+1,j1+Gi+1,j+1+(Gi1,j +
Gi,j1 + Gi,j+1+Gi+1,j )]
Block diagram of VLSI Architecture:
Advantages:

Compared with previous low-complexity design

Low cost and better quality
Low power consumption
High performance
High speed
A hardware sharing technique was used to reduce the hardware
costs of three interpolators