FET BIASING

DC Analysis of JFET Circuits

FET BIASING
Theinput controlling variable for a BJT
transistor is a current level, whereas for the
FET a voltage is the controlling variable.
Important Relationships
IG 0 A
ID = IS
VGS 2
ID = IDSS (1 )
VP
Important Relationships
The
solution can be determined using a
mathematical or graphical approach
 FIXED-BIAS CONFIGURATION
Simplest
of biasing
arrangements for the n-
channel JFET.
Example:
Determine the following for the
network:
a.
b.
c.
d.
e.
f.
 SELF-BIAS CONFIGURATION
Eliminates the need for two dc
supplies.
The controlling gate-to-source
voltage is now determined by
the voltage across
Example:
Determine the following for the
network:
a.
b.
c.
d.
e.
f.
 VOLTAGE-DIVIDER BIASING
The basic
construction is
exactly the same
with BJT but the dc
analysis is quite
different.
Example:
Determine the following for the
network:
a.
b.
c.
d.
e.