GPIO

Featues
All signals of GPIO
Connection of signals on a port
Flowchart input and output of GPIO
 GPIO (General Purpose I/O)
 GPIO include two components:
 GPIO 0 (0x3000_0000)
 GPIO 1 (0x3000_5000)

 Each port has three signals: (N is a, b, c or d)

 GPIO_ext_port N.
 GPIO_port N _ddr.
 GPIO_port N_dr.
Address of GPIO registers
• .EQU dpA, 0x30000004 ; direction of port A,GPIO_0
• .EQU dpB, 0x30000010 ; direction of port B,GPIO_0
• .EQU dpC, 0x3000001c ; direction of port C,GPIO_0
• .EQU dpD, 0x30000028 ; direction of port D,GPIO_0
• .EQU dpE, 0x30005004 ; direction of port A, GPIO_1
• .EQU dpF, 0x30005010 ; direction of port B, GPIO_1

• .EQU ipA,0x30000050 ; input port A address,GPIO_0

• .EQU ipB,0x30000054 ; input port B address,GPIO_0
• .EQU ipC,0x30000058 ; input port C address,GPIO_0
• .EQU ipD, 0x3000005c ; input port D address,GPIO_0
• .EQU ipE,0x30005050 ; input port A address,GPIO_1
• .EQU ipF,0x30005054 ; input port B address,GPIO_1

• .EQU opA, 0x30000000 ; output port A address,GPIO_0

• .EQU opB, 0x3000000c ; output port B address,GPIO_0
• .EQU opC, 0x30000018 ; output port C address,GPIO_0
• .EQU opD, 0x30000024 ; output port D address,GPIO_0
• .EQU opE, 0x30005000 ; output port A address,GPIO_1
• .EQU opF, 0x3000500c ; output port B address,GPIO_1
UART

UART in system
UART pins diagram
Baud Rate & Data Frame
The basic steps set UART
UART in system
 UART _ Features

 VN1632 has two UART peripherals:

 UART0 (address: 0x3000 A000)
 UART1 (address: 0x3000 B000)

 Each UART has the outstanding following features:

 Receiver and Transmitter FIFO with 16 stage depth.
 Transmitter Hold Register Empty (THRE) interrupt mode.
 Stop bit can be 1, 1.5 or 2 bits.
 Receiving and transmitting Break Character.
UART pins diagram
UART_Baud Rate
UART – The Data Frame
The basic steps set UART
Generation for Interrupt generation when
Programmable THRE not in programmable THRE
Interrupt Mode Interrupt Mode
Example:
No limit bytes transfer.

Use FIFO and interrupt for

transmit & receive data.

?
TIMER

Featues
All signals of TIMER
TIMER registers
TIMER usage flow
 TIMER – Featues
TIMER includes two components:
•TIMER 1 (address: 0x3000_C000)
•TIMER 2 (address: 0x3000_C014)

TIMER
block
diagram
All signals of TIMER
 TIMER – registers
– TimersIntStatus (Timers Interrupt Status)
– TimersEOI (Timers End-of-interrupt Register)
– TimersRawIntStatus (Timers Raw Interrupt Status Register)

• Timer 1:
– Timer1LoadCount (Timer 1 Load Count Register)
– Timer1CurrentValue (Timer 1 Current Value Register)
– Timer1ControlReg (Timer 1 Control Register)
– Timer1EOI (Timer 1 End of Interrupt Register)

• Timer 2:
• Timer2LoadCount (Timer 2 Load Count Register)
• Timer2CurrentValue (Timer 2 Current Value Register)
• Timer2ControlReg (Timer 2 Control Register)
• Timer2EOI (Timer 2 End of Interrupt Register)
TIMER
usage
flow
I2C

Featues
I2C Connection
Configuration I2C module as a slave/master
Receive and Transmit data
I2C in system
Featues

I2C = Inter – Intergrated Circuit

 Two-wire I2C serial interface:

 A serial data line (SDA).
 A serial clock (SCL).

 Two speeds:
 Standard mode (100 Kb/s) .
 Fast mode (400 Kb/s).

 Master or Slaver I2C operation:

 7- or 10-bit addressing.
 7- or 10-bit combined format transfers.
I2C connection
Data transfer on I2C bus

START, REPEATED STAR and STOP conditions

7-bit Address Format

10-bit Address Format

I2C module configuration after RESET system.

• Supports Fast mode (400 kb/s).

• Clock synchronization.

• Master I2C operation 10-bit addressing and 10-bit combined format

transfers.

• Bulk transmit mode.

• Transmit and receive buffers.

• Interrupt or polled-mode operation.

• Handles Bit and Byte waiting at all bus speeds.

Configuration
I2C module as
a slave
Configuration
I2C module as
a master
?
I2S

I2S in system
I2S pins diagram
Simple System Configurations for I2S module
I2S module as transmister/receiver
I2S in system
I2S - Featues

The Inter-IC Sound (I2S) Bus is a simple three-wire serial bus

protocol developed by Philips to transfer stereo audio data.
• Sclk: serial clock
• Ws: word select
• Sd: serial data
I2S pins diagram
Simple System Configurations
for I2S module
I2S Stereo Frame Format
Usage flow I2S module Usage flow I2S module
as transmitter as receiver
Thank you for your attention